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TestDesign.vhd 682B

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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. entity TestDesign is
  5. port (
  6. clk : in std_logic;
  7. resetn : in std_logic;
  8. sel : in std_logic_vector(1 downto 0);
  9. we : out std_logic_vector(3 downto 0)
  10. );
  11. end entity TestDesign;
  12. architecture rtl of TestDesign is
  13. begin
  14. process (CLK, RESETn) is
  15. begin
  16. if (RESETn = '0') then
  17. we <= (others => '0');
  18. elsif (rising_edge(CLK)) then
  19. we(0) <= '0' when sel = "00" else '1';
  20. we(1) <= '0' when sel = "01" else '1';
  21. we(2) <= '0' when sel = "10" else '1';
  22. we(3) <= '0' when sel = "11" else '1';
  23. end if;
  24. end process;
  25. end architecture;