diff --git a/pyuvm_tests/Makefile b/pyuvm_tests/Makefile
index 2e0f1e4..775ac2e 100644
--- a/pyuvm_tests/Makefile
+++ b/pyuvm_tests/Makefile
@@ -5,14 +5,24 @@ DUT ?= aes
 EXT := ../ext
 
 ifeq (${DUT}, wishbone)
-  TOPLEVEL := wishboneslavee
-  SIM_ARGS := -gSimulation=true \
-    -gAddressWidth=8 \
-    -gDataWidth=16
+TOPLEVEL := wishboneslavee
+SIM_ARGS := -gSimulation=true \
+-gAddressWidth=8 \
+-gDataWidth=16
 else
-  TOPLEVEL := ${DUT}
+TOPLEVEL := ${DUT}
 endif
 
+ifeq (check, $(firstword $(MAKECMDGOALS)))
+ifeq (FIX, $(lastword $(MAKECMDGOALS)))
+RUFF_ARGS := --fix
+endif
+endif
+
+.PHONY: 
+FIX:
+	@#
+
 # Cocotb related
 MODULE              := tb_${DUT}
 COCOTB_LOG_LEVEL    := DEBUG
@@ -24,28 +34,41 @@ SIM                  ?= ghdl
 TOPLEVEL_LANG        := vhdl
 VHDL_SOURCES_libvhdl := ${EXT}/libvhdl/common/UtilsP.vhd
 VHDL_SOURCES         := ${EXT}/libvhdl/syn/*  \
-  ${EXT}/cryptocores/aes/rtl/vhdl/*.vhd
+${EXT}/cryptocores/aes/rtl/vhdl/*.vhd
 SIM_BUILD            := build
 
 ifeq (${SIM}, ghdl)
-  COMPILE_ARGS := --std=08
-  SIM_ARGS             += \
-    --wave=results/${MODULE}.ghw \
-    --psl-report=results/${MODULE}_psl.json \
-    --vpi-trace=results/${MODULE}_vpi.log
+COMPILE_ARGS := --std=08
+SIM_ARGS             += \
+--wave=results/${MODULE}.ghw \
+--psl-report=results/${MODULE}_psl.json \
+--vpi-trace=results/${MODULE}_vpi.log
 else
-  EXTRA_ARGS := --std=08
-  VHDL_LIB_ORDER := libvhdl
+EXTRA_ARGS := --std=08
+VHDL_LIB_ORDER := libvhdl
 endif
 
 
+check format:
+ifneq (, $(shell which ruff))
+	ruff $@ *.py $(RUFF_ARGS)
+else
+	@echo "ERROR: ruff not found"; exit 1
+endif
+
+
+ifneq (, $(shell which cocotb-config))
 include $(shell cocotb-config --makefiles)/Makefile.sim
+else
+$(warning WARNING: cocotb not found)
+endif
 
 
 results:
 	mkdir -p results
 
 
-.PHONY: clean
 clean::
 	rm -rf *.o __pycache__ uarttx uartrx wishboneslavee aes results $(SIM_BUILD)
+
+.PHONY: clean check format FIX