diff --git a/tests/Makefile b/tests/Makefile
index c6a32f9..aa20c16 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -19,18 +19,24 @@ COCOTB_LOG_LEVEL    := DEBUG
 CUSTOM_COMPILE_DEPS := results
 COCOTB_RESULTS_FILE := results/${MODULE}.xml
 
-# Simulator (GHDL) & RTL related
-SIM                  := ghdl
+# Simulator & RTL related
+SIM                  ?= ghdl
 TOPLEVEL_LANG        := vhdl
 VHDL_SOURCES_libvhdl := ${EXT}/libvhdl/common/UtilsP.vhd
-VHDL_SOURCES         := ${EXT}/libvhdl/syn/*.vhd \
+VHDL_SOURCES         := ${EXT}/libvhdl/syn/*  \
   ${EXT}/cryptocores/aes/rtl/vhdl/*.vhd
-SIM_BUILD            := work
-COMPILE_ARGS         := --std=08
-SIM_ARGS             += \
-  --wave=results/${MODULE}.ghw \
-  --psl-report=results/${MODULE}_psl.json \
-  --vpi-trace=results/${MODULE}_vpi.log
+SIM_BUILD            := build
+
+ifeq (${SIM}, ghdl)
+  COMPILE_ARGS := --std=08
+  SIM_ARGS             += \
+    --wave=results/${MODULE}.ghw \
+    --psl-report=results/${MODULE}_psl.json \
+    --vpi-trace=results/${MODULE}_vpi.log
+else
+  EXTRA_ARGS := --std=08
+  VHDL_LIB_ORDER := libvhdl
+endif
 
 
 include $(shell cocotb-config --makefiles)/Makefile.sim
@@ -42,4 +48,4 @@ results:
 
 .PHONY: clean
 clean::
-	rm -rf *.o __pycache__ uarttx uartrx wishboneslavee aes results
+	rm -rf *.o __pycache__ uarttx uartrx wishboneslavee aes results $(SIM_BUILD)