From d032d83d6399fe426d7f7707000df99f8074da8a Mon Sep 17 00:00:00 2001 From: tmeissner Date: Fri, 11 Feb 2022 16:46:42 +0100 Subject: [PATCH] Remove non-needed imports & ReadOnly() calls --- tests/Sram.py | 3 +-- tests/Uart.py | 6 +----- tests/Vai.py | 4 +--- tests/tb_aes.py | 5 +---- tests/tb_uartrx.py | 6 +++--- tests/tb_uarttx.py | 6 +++--- tests/tb_wishbone.py | 4 +++- 7 files changed, 13 insertions(+), 21 deletions(-) diff --git a/tests/Sram.py b/tests/Sram.py index 9c90dad..0cc22f0 100644 --- a/tests/Sram.py +++ b/tests/Sram.py @@ -1,7 +1,7 @@ import logging import cocotb from cocotb.utils import get_sim_time -from cocotb.triggers import FallingEdge, RisingEdge, Timer, ReadOnly +from cocotb.triggers import FallingEdge, RisingEdge, Timer class Sram: @@ -111,7 +111,6 @@ class SramMonitor(Sram): elif self._ren.value: _adr = self._adr.value await self._clkedge - await ReadOnly() self._transactions[str(get_sim_time('ns'))] = { "type" : "read", "adr" : _adr, diff --git a/tests/Uart.py b/tests/Uart.py index 01aa4d1..32e5e0e 100644 --- a/tests/Uart.py +++ b/tests/Uart.py @@ -1,5 +1,5 @@ import logging -from cocotb.triggers import FallingEdge, RisingEdge, Timer, ReadOnly +from cocotb.triggers import FallingEdge, RisingEdge, Timer class Uart: @@ -53,7 +53,6 @@ class UartReceiver(Uart): self._rec = 0 for x in range(self._bits): await self._wait_cycle() - await ReadOnly() self._rec |= bool(self._txrx.value.integer) << x if self._par: @@ -70,21 +69,18 @@ class UartReceiver(Uart): """Consume and check start bit""" for x in range(int(self._div/2)): await self._clkedge - await ReadOnly() if self._txrx.value == 1: self.log.warning("Start bit set") async def _get_stop_bit(self): """Consume and check stop bit""" await self._wait_cycle() - await ReadOnly() if self._txrx.value == 0: self.log.warning("Stop bit not set") async def _get_parity_bit(self): """Consume and check parity bit""" await self._wait_cycle() - await ReadOnly() if self.odd_parity(self._rec) != self._txrx.value: self.log.warning("Parity wrong") diff --git a/tests/Vai.py b/tests/Vai.py index 8a89d07..f5d6b4d 100644 --- a/tests/Vai.py +++ b/tests/Vai.py @@ -1,7 +1,7 @@ import logging import cocotb from cocotb.utils import get_sim_time -from cocotb.triggers import FallingEdge, RisingEdge, Timer, ReadOnly +from cocotb.triggers import FallingEdge, RisingEdge, Timer class Vai: @@ -56,7 +56,6 @@ class VaiDriver(Vai): self.log.info(f"Send data: {_info}") while True: - await ReadOnly() if self._accept.value: break await self._clkedge @@ -84,7 +83,6 @@ class VaiReceiver(Vai): await self._clkedge while True: - await ReadOnly() if self._valid.value: break await self._clkedge diff --git a/tests/tb_aes.py b/tests/tb_aes.py index 8376f7c..6566b57 100644 --- a/tests/tb_aes.py +++ b/tests/tb_aes.py @@ -1,13 +1,10 @@ import logging -import random import cocotb -import pprint from Vai import VaiDriver, VaiReceiver, VaiMonitor from cocotb.clock import Clock from cocotb.queue import Queue -from cocotb.triggers import FallingEdge, RisingEdge, Timer, ReadOnly +from cocotb.triggers import RisingEdge, Timer from Crypto.Cipher import AES -from Crypto.Util.number import long_to_bytes, getRandomNBitInteger import vsc diff --git a/tests/tb_uartrx.py b/tests/tb_uartrx.py index 6f83b0c..14ef269 100644 --- a/tests/tb_uartrx.py +++ b/tests/tb_uartrx.py @@ -1,10 +1,10 @@ import logging import random import cocotb -from Uart import UartDriver, UartReceiver -from Vai import VaiDriver, VaiReceiver +from Uart import UartDriver +from Vai import VaiReceiver from cocotb.clock import Clock -from cocotb.triggers import FallingEdge, RisingEdge, Timer, ReadOnly +from cocotb.triggers import RisingEdge, Timer # Reset coroutine diff --git a/tests/tb_uarttx.py b/tests/tb_uarttx.py index b176ee6..2f81abc 100644 --- a/tests/tb_uarttx.py +++ b/tests/tb_uarttx.py @@ -1,10 +1,10 @@ import logging import random import cocotb -from Uart import UartDriver, UartReceiver -from Vai import VaiDriver, VaiReceiver +from Uart import UartReceiver +from Vai import VaiDriver from cocotb.clock import Clock -from cocotb.triggers import FallingEdge, RisingEdge, Timer, ReadOnly +from cocotb.triggers import RisingEdge, Timer # Reset coroutine diff --git a/tests/tb_wishbone.py b/tests/tb_wishbone.py index 09fa7e0..6a53694 100644 --- a/tests/tb_wishbone.py +++ b/tests/tb_wishbone.py @@ -5,7 +5,7 @@ import wavedrom from collections import defaultdict from Sram import SramRead, SramWrite, SramMonitor from cocotb.clock import Clock -from cocotb.triggers import FallingEdge, RisingEdge, Timer, ReadOnly +from cocotb.triggers import RisingEdge, Timer from cocotbext.wishbone.driver import WishboneMaster, WBOp from cocotb.wavedrom import Wavedrom, trace @@ -77,6 +77,8 @@ async def test_wishbone(dut): data = random.randint(0, 2**16-1) await wbmaster.send_cycle([WBOp(adr=adr, dat=data)]) rec = await wbmaster.send_cycle([WBOp(adr=adr)]) + assert rec[0].datrd == data, \ + f"Read data incorrect, got {hex(rec[0].datrd)}, expected {hex(data)}" # Print out waveforms as json & svg _wave = waves.dumpj()