cryptography ip-cores in vhdl / verilog
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  1. -- ======================================================================
  2. -- AES Counter mode testbench
  3. -- Copyright (C) 2020 Torsten Meissner
  4. -------------------------------------------------------------------------
  5. -- This program is free software; you can redistribute it and/or modify
  6. -- it under the terms of the GNU General Public License as published by
  7. -- the Free Software Foundation; either version 2 of the License, or
  8. -- (at your option) any later version.
  9. -- This program is distributed in the hope that it will be useful,
  10. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. -- GNU General Public License for more details.
  13. -- You should have received a copy of the GNU General Public License
  14. -- along with this program; if not, write to the Free Software
  15. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  16. -- ======================================================================
  17. library ieee;
  18. use ieee.std_logic_1164.all;
  19. use ieee.numeric_std.all;
  20. library osvvm;
  21. use osvvm.RandomPkg.all;
  22. use std.env.all;
  23. entity tb_ctraes is
  24. end entity tb_ctraes;
  25. architecture sim of tb_ctraes is
  26. constant C_NONCE_WIDTH : natural range 64 to 96 := 96;
  27. signal s_reset : std_logic := '0';
  28. signal s_clk : std_logic := '0';
  29. signal s_start : std_logic := '0';
  30. signal s_nonce : std_logic_vector(0 to C_NONCE_WIDTH-1) := (others => '0');
  31. signal s_key : std_logic_vector(0 to 127) := (others => '0');
  32. signal s_datain : std_logic_vector(0 to 127) := (others => '0');
  33. signal s_validin : std_logic := '0';
  34. signal s_acceptin : std_logic;
  35. signal s_dataout : std_logic_vector(0 to 127);
  36. signal s_validout : std_logic := '0';
  37. signal s_acceptout : std_logic := '0';
  38. procedure cryptData(datain : in std_logic_vector(0 to 127);
  39. key : in std_logic_vector(0 to 127);
  40. iv : in std_logic_vector(0 to 127);
  41. start : in boolean;
  42. final : in boolean;
  43. dataout : out std_logic_vector(0 to 127);
  44. bytelen : in integer) is
  45. begin
  46. report "VHPIDIRECT cryptData" severity failure;
  47. end procedure;
  48. attribute foreign of cryptData: procedure is "VHPIDIRECT cryptData";
  49. function swap (datain : std_logic_vector(0 to 127)) return std_logic_vector is
  50. variable v_data : std_logic_vector(0 to 127);
  51. begin
  52. for i in 0 to 15 loop
  53. for y in 0 to 7 loop
  54. v_data((i*8)+y) := datain((i*8)+7-y);
  55. end loop;
  56. end loop;
  57. return v_data;
  58. end function;
  59. begin
  60. i_ctraes : entity work.ctraes
  61. generic map (
  62. NONCE_WIDTH => C_NONCE_WIDTH
  63. )
  64. port map (
  65. reset_i => s_reset,
  66. clk_i => s_clk,
  67. start_i => s_start,
  68. nonce_i => s_nonce,
  69. key_i => s_key,
  70. data_i => s_datain,
  71. valid_i => s_validin,
  72. accept_o => s_acceptin,
  73. data_o => s_dataout,
  74. valid_o => s_validout,
  75. accept_i => s_acceptout
  76. );
  77. s_clk <= not(s_clk) after 10 ns;
  78. s_reset <= '1' after 100 ns;
  79. process is
  80. variable v_start : std_logic;
  81. variable v_key : std_logic_vector(0 to 127);
  82. variable v_nonce : std_logic_vector(0 to C_NONCE_WIDTH-1);
  83. variable v_datain : std_logic_vector(0 to 127);
  84. variable v_dataout : std_logic_vector(0 to 127);
  85. variable v_random : RandomPType;
  86. begin
  87. v_random.InitSeed(v_random'instance_name);
  88. wait until s_reset = '1' and rising_edge(s_clk);
  89. -- ENCRYPTION TESTs
  90. report "Test CTR-AES encryption";
  91. for i in 0 to 31 loop
  92. if (i = 0) then
  93. v_start := '1';
  94. v_nonce := v_random.RandSlv(s_nonce'length);
  95. else
  96. v_start := '0';
  97. end if;
  98. v_key := v_random.RandSlv(128);
  99. v_datain := v_random.RandSlv(128);
  100. s_key <= v_key;
  101. s_validin <= '1';
  102. s_start <= v_start;
  103. s_nonce <= v_nonce;
  104. s_datain <= v_datain;
  105. cryptData(swap(v_datain), swap(v_key), swap(v_nonce & 32x"0"), i = 0, i = 31, v_dataout, v_datain'length/8);
  106. wait until s_acceptin = '1' and rising_edge(s_clk);
  107. s_validin <= '0';
  108. wait until s_validout = '1' and rising_edge(s_clk);
  109. s_acceptout <= '1';
  110. assert s_dataout = swap(v_dataout)
  111. report "Encryption error: Expected 0x" & to_hstring(swap(v_dataout)) & ", got 0x" & to_hstring(s_dataout)
  112. severity failure;
  113. wait until rising_edge(s_clk);
  114. s_acceptout <= '0';
  115. end loop;
  116. -- Watchdog
  117. wait for 100 ns;
  118. finish(0);
  119. end process;
  120. end architecture sim;