diff --git a/des/rtl/verilog/des.v b/des/rtl/verilog/des.v deleted file mode 100644 index e69de29..0000000 diff --git a/des/rtl/vhdl/des.vhd b/des/rtl/vhdl/des.vhd deleted file mode 100644 index 3434143..0000000 --- a/des/rtl/vhdl/des.vhd +++ /dev/null @@ -1,334 +0,0 @@ --- ====================================================================== --- DES encryption/decryption --- algorithm according to FIPS 46-3 specification --- Copyright (C) 2007 Torsten Meissner -------------------------------------------------------------------------- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. - --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. - --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA --- ====================================================================== - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.numeric_std.ALL; -USE work.des_pkg.ALL; - - -ENTITY des IS - PORT ( - reset_i : in std_logic; -- async reset - clk_i : IN std_logic; -- clock - mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt - key_i : IN std_logic_vector(0 TO 63); -- key input - data_i : IN std_logic_vector(0 TO 63); -- data input - valid_i : IN std_logic; -- input key/data valid flag - data_o : OUT std_logic_vector(0 TO 63); -- data output - valid_o : OUT std_logic -- output data valid flag - ); -END ENTITY des; - - -ARCHITECTURE rtl OF des IS - -BEGIN - - crypt : PROCESS ( clk_i ) IS - -- variables for key calculation - VARIABLE c0 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c1 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c2 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c3 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c4 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c5 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c6 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c7 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c8 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c9 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d0 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d1 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d2 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d3 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d4 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d5 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d6 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d7 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d8 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d9 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0'); - -- key variables - VARIABLE key1 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key2 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key3 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key4 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key5 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key6 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key7 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key8 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key9 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0'); - -- variables for left & right data blocks - VARIABLE l0 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l1 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l2 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l3 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l4 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l5 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l6 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l7 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l8 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l9 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r0 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r1 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r2 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r3 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r4 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r5 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r6 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r7 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r8 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r9 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0'); - -- variables for mode & valid shift registers - VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0'); - VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0'); - BEGIN - if(reset_i = '0') then - data_o <= (others => '0'); - valid_o <= '0'; - elsif rising_edge( clk_i ) THEN - -- shift registers - valid(1 TO 17) := valid(0 TO 16); - valid(0) := valid_i; - mode(1 TO 16) := mode(0 TO 15); - mode(0) := mode_i; - -- output stage - valid_o <= valid(17); - data_o <= ipn( ( r16 & l16 ) ); - -- 16. stage - IF mode(16) = '0' THEN - c16 := c15(1 TO 27) & c15(0); - d16 := d15(1 TO 27) & d15(0); - ELSE - c16 := c15(27) & c15(0 TO 26); - d16 := d15(27) & d15(0 TO 26); - END IF; - key16 := pc2( ( c16 & d16 ) ); - l16 := r15; - r16 := l15 xor ( f( r15, key16 ) ); - -- 15. stage - IF mode(15) = '0' THEN - c15 := c14(2 TO 27) & c14(0 TO 1); - d15 := d14(2 TO 27) & d14(0 TO 1); - ELSE - c15 := c14(26 TO 27) & c14(0 TO 25); - d15 := d14(26 TO 27) & d14(0 TO 25); - END IF; - key15 := pc2( ( c15 & d15 ) ); - l15 := r14; - r15 := l14 xor ( f( r14, key15 ) ); - -- 14. stage - IF mode(14) = '0' THEN - c14 := c13(2 TO 27) & c13(0 TO 1); - d14 := d13(2 TO 27) & d13(0 TO 1); - ELSE - c14 := c13(26 TO 27) & c13(0 TO 25); - d14 := d13(26 TO 27) & d13(0 TO 25); - END IF; - key14 := pc2( ( c14 & d14 ) ); - l14 := r13; - r14 := l13 xor ( f( r13, key14 ) ); - -- 13. stage - IF mode(13) = '0' THEN - c13 := c12(2 TO 27) & c12(0 TO 1); - d13 := d12(2 TO 27) & d12(0 TO 1); - ELSE - c13 := c12(26 TO 27) & c12(0 TO 25); - d13 := d12(26 TO 27) & d12(0 TO 25); - END IF; - key13 := pc2( ( c13 & d13 ) ); - l13 := r12; - r13 := l12 xor ( f( r12, key13 ) ); - -- 12. stage - IF mode(12) = '0' THEN - c12 := c11(2 TO 27) & c11(0 TO 1); - d12 := d11(2 TO 27) & d11(0 TO 1); - ELSE - c12 := c11(26 TO 27) & c11(0 TO 25); - d12 := d11(26 TO 27) & d11(0 TO 25); - END IF; - key12 := pc2( ( c12 & d12 ) ); - l12 := r11; - r12 := l11 xor ( f( r11, key12 ) ); - -- 11. stage - IF mode(11) = '0' THEN - c11 := c10(2 TO 27) & c10(0 TO 1); - d11 := d10(2 TO 27) & d10(0 TO 1); - ELSE - c11 := c10(26 TO 27) & c10(0 TO 25); - d11 := d10(26 TO 27) & d10(0 TO 25); - END IF; - key11 := pc2( ( c11 & d11 ) ); - l11 := r10; - r11 := l10 xor ( f( r10, key11 ) ); - -- 10. stage - IF mode(10) = '0' THEN - c10 := c9(2 TO 27) & c9(0 TO 1); - d10 := d9(2 TO 27) & d9(0 TO 1); - ELSE - c10 := c9(26 TO 27) & c9(0 TO 25); - d10 := d9(26 TO 27) & d9(0 TO 25); - END IF; - key10 := pc2( ( c10 & d10 ) ); - l10 := r9; - r10 := l9 xor ( f( r9, key10 ) ); - -- 9. stage - IF mode(9) = '0' THEN - c9 := c8(1 TO 27) & c8(0); - d9 := d8(1 TO 27) & d8(0); - ELSE - c9 := c8(27) & c8(0 TO 26); - d9 := d8(27) & d8(0 TO 26); - END IF; - key9 := pc2( ( c9 & d9 ) ); - l9 := r8; - r9 := l8 xor ( f( r8, key9 ) ); - -- 8. stage - IF mode(8) = '0' THEN - c8 := c7(2 TO 27) & c7(0 TO 1); - d8 := d7(2 TO 27) & d7(0 TO 1); - ELSE - c8 := c7(26 TO 27) & c7(0 TO 25); - d8 := d7(26 TO 27) & d7(0 TO 25); - END IF; - key8 := pc2( ( c8 & d8 ) ); - l8 := r7; - r8 := l7 xor ( f( r7, key8 ) ); - -- 7. stage - IF mode(7) = '0' THEN - c7 := c6(2 TO 27) & c6(0 TO 1); - d7 := d6(2 TO 27) & d6(0 TO 1); - ELSE - c7 := c6(26 TO 27) & c6(0 TO 25); - d7 := d6(26 TO 27) & d6(0 TO 25); - END IF; - key7 := pc2( ( c7 & d7 ) ); - l7 := r6; - r7 := l6 xor ( f( r6, key7 ) ); - -- 6. stage - IF mode(6) = '0' THEN - c6 := c5(2 TO 27) & c5(0 TO 1); - d6 := d5(2 TO 27) & d5(0 TO 1); - ELSE - c6 := c5(26 TO 27) & c5(0 TO 25); - d6 := d5(26 TO 27) & d5(0 TO 25); - END IF; - key6 := pc2( ( c6 & d6 ) ); - l6 := r5; - r6 := l5 xor ( f( r5, key6 ) ); - -- 5. stage - IF mode(5) = '0' THEN - c5 := c4(2 TO 27) & c4(0 TO 1); - d5 := d4(2 TO 27) & d4(0 TO 1); - ELSE - c5 := c4(26 TO 27) & c4(0 TO 25); - d5 := d4(26 TO 27) & d4(0 TO 25); - END IF; - key5 := pc2( ( c5 & d5 ) ); - l5 := r4; - r5 := l4 xor ( f( r4, key5 ) ); - -- 4. stage - IF mode(4) = '0' THEN - c4 := c3(2 TO 27) & c3(0 TO 1); - d4 := d3(2 TO 27) & d3(0 TO 1); - ELSE - c4 := c3(26 TO 27) & c3(0 TO 25); - d4 := d3(26 TO 27) & d3(0 TO 25); - END IF; - key4 := pc2( ( c4 & d4 ) ); - l4 := r3; - r4 := l3 xor ( f( r3, key4 ) ); - -- 3. stage - IF mode(3) = '0' THEN - c3 := c2(2 TO 27) & c2(0 TO 1); - d3 := d2(2 TO 27) & d2(0 TO 1); - ELSE - c3 := c2(26 TO 27) & c2(0 TO 25); - d3 := d2(26 TO 27) & d2(0 TO 25); - END IF; - key3 := pc2( ( c3 & d3 ) ); - l3 := r2; - r3 := l2 xor ( f( r2, key3 ) ); - -- 2. stage - IF mode(2) = '0' THEN - c2 := c1(1 TO 27) & c1(0); - d2 := d1(1 TO 27) & d1(0); - ELSE - c2 := c1(27) & c1(0 TO 26); - d2 := d1(27) & d1(0 TO 26); - END IF; - key2 := pc2( ( c2 & d2 ) ); - l2 := r1; - r2 := l1 xor ( f( r1, key2 ) ); - -- 1. stage - IF mode(1) = '0' THEN - c1 := c0(1 TO 27) & c0(0); - d1 := d0(1 TO 27) & d0(0); - ELSE - c1 := c0; - d1 := d0; - END IF; - key1 := pc2( ( c1 & d1 ) ); - l1 := r0; - r1 := l0 xor ( f( r0, key1 ) ); - -- input stage - l0 := ip( data_i )(0 TO 31); - r0 := ip( data_i )(32 TO 63); - c0 := pc1_c( key_i ); - d0 := pc1_d( key_i ); - END IF; - END PROCESS crypt; - -END ARCHITECTURE rtl; diff --git a/des/rtl/vhdl/des_pkg.vhd b/des/rtl/vhdl/des_pkg.vhd deleted file mode 100644 index d88e91f..0000000 --- a/des/rtl/vhdl/des_pkg.vhd +++ /dev/null @@ -1,333 +0,0 @@ --- ====================================================================== --- DES encryption/decryption --- package file with functions --- Copyright (C) 2007 Torsten Meissner -------------------------------------------------------------------------- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. - --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. - --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA --- ====================================================================== - - --- Revision 1.0 2007/02/04 --- Initial release - - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.numeric_std.ALL; - - -PACKAGE des_pkg IS - - FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - - FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; - FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; - - FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - - FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector; - - FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector; - -END PACKAGE des_pkg; - - -PACKAGE BODY des_pkg IS - - FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63; - VARIABLE table : matrix := (57, 49, 41, 33, 25, 17, 9, 1, - 59, 51, 43, 35, 27, 19, 11, 3, - 61, 53, 45, 37, 29, 21, 13, 5, - 63, 55, 47, 39, 31, 23, 15, 7, - 56, 48, 40, 32, 24, 16, 8, 0, - 58, 50, 42, 34, 26, 18, 10, 2, - 60, 52, 44, 36, 28, 20, 12, 4, - 62, 54, 46, 38, 30, 22, 14, 6); - VARIABLE result : std_logic_vector(0 TO 63); - BEGIN - FOR index IN 0 TO 63 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION ip; - - FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63; - VARIABLE table : matrix := (39, 7, 47, 15, 55, 23, 63, 31, - 38, 6, 46, 14, 54, 22, 62, 30, - 37, 5, 45, 13, 53, 21, 61, 29, - 36, 4, 44, 12, 52, 20, 60, 28, - 35, 3, 43, 11, 51, 19, 59, 27, - 34, 2, 42, 10, 50, 18, 58, 26, - 33, 1, 41, 9, 49, 17, 57, 25, - 32, 0, 40, 8, 48, 16, 56, 24); - VARIABLE result : std_logic_vector(0 TO 63); - BEGIN - FOR index IN 0 TO 63 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION ipn; - - FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31; - VARIABLE table : matrix := (31, 0, 1, 2, 3, 4, - 3, 4, 5, 6, 7, 8, - 7, 8, 9, 10, 11, 12, - 11, 12, 13, 14, 15, 16, - 15, 16, 17, 18, 19, 20, - 19, 20, 21, 22, 23, 24, - 23, 24, 25, 26, 27, 28, - 27, 28, 29, 30, 31, 0); - VARIABLE result : std_logic_vector(0 TO 47); - BEGIN - FOR index IN 0 TO 47 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION e; - - FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => (14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7), - 1 => ( 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8), - 2 => ( 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0), - 3 => (15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s1; - - FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => (15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10), - 1 => ( 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5), - 2 => ( 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15), - 3 => (13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s2; - - FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => (10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8), - 1 => (13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1), - 2 => (13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7), - 3 => ( 1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s3; - - FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => ( 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15), - 1 => (13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9), - 2 => (10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4), - 3 => ( 3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s4; - - FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => ( 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9), - 1 => (14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6), - 2 => ( 4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14), - 3 => (11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s5; - - FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => (12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11), - 1 => (10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8), - 2 => ( 9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6), - 3 => ( 4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s6; - - FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => ( 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1), - 1 => (13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6), - 2 => ( 1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2), - 3 => ( 6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s7; - - FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => (13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7), - 1 => ( 1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2), - 2 => ( 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8), - 3 => ( 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s8; - - FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31; - VARIABLE table : matrix := (15, 6, 19, 20, - 28, 11, 27, 16, - 0, 14, 22, 25, - 4, 17, 30, 9, - 1, 7, 23, 13, - 31, 26, 2, 8, - 18, 12, 29, 5, - 21, 10, 3, 24); - VARIABLE result : std_logic_vector(0 TO 31); - BEGIN - FOR index IN 0 TO 31 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION p; - - FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS - VARIABLE intern : std_logic_vector(0 TO 47); - VARIABLE result : std_logic_vector(0 TO 31); - BEGIN - intern := e( input_r ) xor input_key; - result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) & - s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) ); - RETURN result; - END FUNCTION f; - - FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63; - VARIABLE table : matrix := (56, 48, 40, 32, 24, 16, 8, - 0, 57, 49, 41, 33, 25, 17, - 9, 1, 58, 50, 42, 34, 26, - 18, 10, 2, 59, 51, 43, 35); - VARIABLE result : std_logic_vector(0 TO 27); - BEGIN - FOR index IN 0 TO 27 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc1_c; - - FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63; - VARIABLE table : matrix := (62, 54, 46, 38, 30, 22, 14, - 6, 61, 53, 45, 37, 29, 21, - 13, 5, 60, 52, 44, 36, 28, - 20, 12, 4, 27, 19, 11, 3); - VARIABLE result : std_logic_vector(0 TO 27); - BEGIN - FOR index IN 0 TO 27 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc1_d; - - FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63; - VARIABLE table : matrix := (13, 16, 10, 23, 0, 4, - 2, 27, 14, 5, 20, 9, - 22, 18, 11, 3, 25, 7, - 15, 6, 26, 19, 12, 1, - 40, 51, 30, 36, 46, 54, - 29, 39, 50, 44, 32, 47, - 43, 48, 38, 55, 33, 52, - 45, 41, 49, 35, 28, 31); - VARIABLE result : std_logic_vector(0 TO 47); - BEGIN - FOR index IN 0 TO 47 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc2; - - -END PACKAGE BODY des_pkg;