diff --git a/cbcdes/sim/makefile b/cbcdes/sim/makefile index 2cac600..84dd194 100644 --- a/cbcdes/sim/makefile +++ b/cbcdes/sim/makefile @@ -19,29 +19,11 @@ # ====================================================================== -# enable the compile of the OVL library -# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory -OVL_ENABLE = 0 - -# the location and sources of the OVL library (copyright of Accellera) -# OVL is not included in this project, you can download it from -# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/ -OVL_LOC = ../../../../OVL/ -ifeq ($(OVL_ENABLE), 1) - OVL_SRC = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \ - $(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \ - $(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \ - $(OVL_LOC)/vhdl93/ovl_*_rtl.vhd -else - OVL_SRC = -endif - all : sim wave sim : tb_cbcdes.ghw -tb_cbcdes.ghw : ../rtl/*.vhd tb_cbcdes.vhd $(OVL_SRC) - ghdl -a $(OVL_SRC) +tb_cbcdes.ghw : ../rtl/*.vhd tb_cbcdes.vhd ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/cbcdes.vhd tb_cbcdes.vhd ghdl -e tb_cbcdes ghdl -r tb_cbcdes --wave=tb_cbcdes.ghw --assert-level=error --stop-time=220us diff --git a/cbctdes/sim/makefile b/cbctdes/sim/makefile index d68e3b9..2b49100 100644 --- a/cbctdes/sim/makefile +++ b/cbctdes/sim/makefile @@ -19,30 +19,11 @@ # ====================================================================== -# enable the compile of the OVL library -# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory -OVL_ENABLE = 0 - -# the location and sources of the OVL library (copyright of Accellera) -# OVL is not included in this project, you can download it from -# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/ -OVL_LOC = ../../../../OVL/ -ifeq ($(OVL_ENABLE), 1) - OVL_SRC = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \ - $(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \ - $(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \ - $(OVL_LOC)/vhdl93/ovl_*_rtl.vhd -else - OVL_SRC = -endif - - all : sim wave sim : tb_cbctdes.ghw -tb_cbctdes.ghw : ../rtl/*.vhd tb_cbctdes.vhd $(OVL_SRC) - ghdl -a $(OVL_SRC) +tb_cbctdes.ghw : ../rtl/*.vhd tb_cbctdes.vhd ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/tdes.vhd ../rtl/cbctdes.vhd tb_cbctdes.vhd ghdl -e tb_cbctdes ghdl -r tb_cbctdes --wave=tb_cbctdes.ghw --assert-level=error --stop-time=45us diff --git a/des/rtl/des.vhd b/des/rtl/des.vhd index 9ebc905..3434143 100644 --- a/des/rtl/des.vhd +++ b/des/rtl/des.vhd @@ -19,12 +19,6 @@ -- ====================================================================== --- Revision 1.0 2007/02/04 --- Initial release --- Revision 1.1 2007/02/05 --- Corrected error in use of mode register for key calculation - - LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.ALL; diff --git a/des/rtl/des_pkg.vhd b/des/rtl/des_pkg.vhd index 384209e..d88e91f 100644 --- a/des/rtl/des_pkg.vhd +++ b/des/rtl/des_pkg.vhd @@ -330,4 +330,4 @@ PACKAGE BODY des_pkg IS END FUNCTION pc2; -END PACKAGE BODY des_pkg; \ No newline at end of file +END PACKAGE BODY des_pkg; diff --git a/des/sim/makefile b/des/sim/makefile index 086c537..5c8a91d 100644 --- a/des/sim/makefile +++ b/des/sim/makefile @@ -19,31 +19,12 @@ # ====================================================================== -# enable the compile of the OVL library -# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory -OVL_ENABLE = 0 - -# the location and sources of the OVL library (copyright of Accellera) -# OVL is not included in this project, you can download it from -# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/ -OVL_LOC = ../../../../OVL/ -ifeq ($(OVL_ENABLE), 1) - OVL_SRC = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \ - $(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \ - $(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \ - $(OVL_LOC)/vhdl93/ovl_*_rtl.vhd -else - OVL_SRC = -endif - - all : sim wave sim : tb_des.ghw -tb_des.ghw : ../rtl/*.vhd tb_des.vhd $(OVL_SRC) - ghdl -a $(OVL_SRC) +tb_des.ghw : ../rtl/*.vhd tb_des.vhd ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd tb_des.vhd ghdl -e tb_des ghdl -r tb_des --wave=tb_des.ghw --assert-level=error --stop-time=11us diff --git a/tdes/sim/makefile b/tdes/sim/makefile index b8e2c5d..1d54344 100644 --- a/tdes/sim/makefile +++ b/tdes/sim/makefile @@ -19,30 +19,11 @@ # ====================================================================== -# enable the compile of the OVL library -# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory -OVL_ENABLE = 0 - -# the location and sources of the OVL library (copyright of Accellera) -# OVL is not included in this project, you can download it from -# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/ -OVL_LOC = ../../../../OVL/ -ifeq ($(OVL_ENABLE), 1) - OVL_SRC = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \ - $(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \ - $(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \ - $(OVL_LOC)/vhdl93/ovl_*_rtl.vhd -else - OVL_SRC = -endif - - all : sim wave sim : tb_tdes.ghw -tb_tdes.ghw : ../rtl/*.vhd tb_tdes.vhd $(OVL_SRC) - ghdl -a $(OVL_SRC) +tb_tdes.ghw : ../rtl/*.vhd tb_tdes.vhd ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/tdes.vhd tb_tdes.vhd ghdl -e tb_tdes ghdl -r tb_tdes --wave=tb_tdes.ghw --assert-level=error --stop-time=45us