diff --git a/aes/rtl/aes_pkg.vhd b/aes/rtl/aes_pkg.vhd
index a16080c..1889d9e 100644
--- a/aes/rtl/aes_pkg.vhd
+++ b/aes/rtl/aes_pkg.vhd
@@ -19,19 +19,43 @@
 -- ======================================================================
 
 
--- Revision 0.1  2011/10/22
--- Initial release
-
-
-
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+library accellera_ovl_vhdl;
+use accellera_ovl_vhdl.std_ovl.all;
+use accellera_ovl_vhdl.std_ovl_procs.all;
 
 package aes_pkg is
 
 
+  -- OVL configuration
+  constant ovl_proj_controls : ovl_ctrl_record := (
+    -- generate statement controls
+    xcheck_ctrl          => OVL_ON, 
+    implicit_xcheck_ctrl => OVL_ON, 
+    init_msg_ctrl        => OVL_ON,
+    init_count_ctrl      => OVL_ON,
+    assert_ctrl          => OVL_ON,
+    cover_ctrl           => OVL_ON,
+    global_reset_ctrl    => OVL_ON,
+    finish_ctrl          => OVL_ON,
+    gating_ctrl          => OVL_ON,
+    -- user configurable library constants
+    max_report_error       => 4,
+    max_report_cover_point => 15,
+    runtime_after_fatal    => "150 ns    ",
+    -- default values for common generics
+    severity_level_default => OVL_SEVERITY_DEFAULT,
+    property_type_default  => OVL_PROPERTY_DEFAULT,
+    msg_default            => ovl_set_msg(""),  -- OVL_MSG_DEFAULT
+    coverage_level_default => OVL_COVER_DEFAULT,
+    clock_edge_default     => OVL_CLOCK_EDGE_DEFAULT,
+    reset_polarity_default => OVL_RESET_POLARITY_DEFAULT,
+    gating_type_default    => OVL_GATING_TYPE_DEFAULT);
+
+
   type t_datatable1d is array (0 to 3) of std_logic_vector(7 downto 0);
   type t_datatable2d is array (0 to 3) of t_datatable1d;
 
diff --git a/aes/sim/makefile b/aes/sim/makefile
index 10555ad..2b95069 100644
--- a/aes/sim/makefile
+++ b/aes/sim/makefile
@@ -21,7 +21,7 @@
 
 # enable the compile of the OVL library
 # if set to 1, you must have the OVL_SRC files in the OVL_LOC directory
-OVL_ENABLE = 0
+OVL_ENABLE = 1
 
 # the location and sources of the OVL library (copyright of Accellera)
 # OVL is not included in this project, you can download it from
@@ -41,7 +41,7 @@ all : sim wave
 sim : tb_aes.ghw
 
 tb_aes.ghw : ../rtl/*.vhd tb_aes.vhd $(OVL_SRC)
-	ghdl -a $(OVL_SRC)
+	ghdl -a --work=accellera_ovl_vhdl $(OVL_SRC)
 	ghdl -a ../rtl/aes_pkg.vhd ../rtl/aes.vhd tb_aes.vhd
 	ghdl -e tb_aes
 	ghdl -r tb_aes --wave=tb_aes.ghw --assert-level=error --stop-time=10us
@@ -52,4 +52,4 @@ wave : tb_aes.ghw
 clean :
 	echo "# cleaning simulation files"
 	rm -f tb_aes.ghw
-	rm -f work*.cf
+	rm -f *.cf