From 62cd1950fe1b3e50a5ce9c34fd810d21d6790cc8 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Sun, 29 Dec 2013 17:12:59 +0100 Subject: [PATCH 1/6] add implementation of mixcolumns function --- aes/rtl/vhdl/aes_pkg.vhd | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/aes/rtl/vhdl/aes_pkg.vhd b/aes/rtl/vhdl/aes_pkg.vhd index 3a0762e..7afeadc 100644 --- a/aes/rtl/vhdl/aes_pkg.vhd +++ b/aes/rtl/vhdl/aes_pkg.vhd @@ -171,7 +171,7 @@ package body aes_pkg is v_hi_bit_set := a(7); v_a := v_a(6 downto 0) & '0'; if(v_hi_bit_set = '1') then - v_a := v_a xor x"01"; + v_a := v_a xor x"01"; end if; v_b := '0' & v_b(7 downto 1); end loop; @@ -180,13 +180,16 @@ package body aes_pkg is -- matrix columns manipulation - -- 02 03 01 01 - -- 01 02 03 01 - -- 01 01 02 03 - -- 03 01 01 02 function mixcolumns (input : t_datatable2d; column : natural) return t_datatable2d is variable v_data : t_datatable2d; begin + for index in 0 to 3 loop + v_data(index)(0) := gmul(x"02",input(index)(0)) xor gmul(x"03",input(index)(1)) xor input(index)(2) xor input(index)(3); + v_data(index)(1) := input(index)(0) xor gmul(x"02",input(index)(1)) xor gmul(x"03",input(index)(2)) xor input(index)(3); + v_data(index)(2) := input(index)(0) xor input(index)(1) xor gmul(x"02",input(index)(2)) xor gmul(x"03",input(index)(3)); + v_data(index)(3) := gmul(x"03", input(index)(0)) xor input(index)(1) xor input(index)(2) xor gmul(x"02",input(index)(3)); + end loop; + return v_data; end function mixcolumns; From 2a2aa23e21c8cec43399a74c7c11618ca2dd9dd4 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Tue, 8 Jul 2014 01:30:56 +0200 Subject: [PATCH 2/6] wait for rising edge of reset before send stimuli data --- cbctdes/sim/verilog/tb_cbctdes.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cbctdes/sim/verilog/tb_cbctdes.v b/cbctdes/sim/verilog/tb_cbctdes.v index 96b44c1..dbb2a74 100644 --- a/cbctdes/sim/verilog/tb_cbctdes.v +++ b/cbctdes/sim/verilog/tb_cbctdes.v @@ -89,6 +89,7 @@ module tb_cbctdes; initial forever @(negedge reset) begin index = 0; + wait (reset); while (index < 19) begin @(posedge clk) if (ready) begin @@ -131,7 +132,7 @@ module tb_cbctdes; // checker process always begin : checker - wait (reset) + wait (reset); outdex = 0; // encryption tests From a91d55740a8ae7e38b52a8255a7ad13467f70dc1 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Tue, 8 Jul 2014 01:31:55 +0200 Subject: [PATCH 3/6] wait for rising edge of s_reset before send stimuli data --- cbctdes/sim/vhdl/tb_cbctdes.vhd | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/cbctdes/sim/vhdl/tb_cbctdes.vhd b/cbctdes/sim/vhdl/tb_cbctdes.vhd index 5e903ed..01b97e1 100644 --- a/cbctdes/sim/vhdl/tb_cbctdes.vhd +++ b/cbctdes/sim/vhdl/tb_cbctdes.vhd @@ -32,7 +32,7 @@ architecture rtl of tb_cbctdes is type t_array is array (natural range <>) of std_logic_vector(0 to 63); - + constant c_table_test_plain : t_array(0 to 18) := (x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172", x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A", @@ -83,7 +83,7 @@ begin s_reset <= '1' after 100 ns; s_clk <= not(s_clk) after 10 ns; - + teststimuliP : process is begin @@ -95,6 +95,7 @@ begin s_key2 <= (others => '0'); s_key3 <= (others => '0'); s_datain <= (others => '0'); + wait until s_reset = '1'; -- ENCRYPTION TESTS -- cbc known answers test for index in c_table_test_plain'range loop @@ -148,8 +149,8 @@ begin s_datain <= (others => '0'); wait; end process teststimuliP; - - + + testcheckerP : process is begin report "# ENCRYPTION TESTS"; @@ -181,10 +182,10 @@ begin key2_i => s_key2, key3_i => s_key3, data_i => s_datain, - valid_i => s_validin, + valid_i => s_validin, data_o => s_dataout, valid_o => s_validout, - ready_o => s_ready + ready_o => s_ready ); From 4b1f3d11f9350c651db665699eb873be34efe9be Mon Sep 17 00:00:00 2001 From: tmeissner Date: Tue, 8 Jul 2014 01:33:19 +0200 Subject: [PATCH 4/6] removed internal synced copy of reset_i; set ready to high in reset --- cbctdes/rtl/verilog/cbctdes.v | 21 +++++++++------------ cbctdes/rtl/verilog/tdes.v | 7 ++----- 2 files changed, 11 insertions(+), 17 deletions(-) diff --git a/cbctdes/rtl/verilog/cbctdes.v b/cbctdes/rtl/verilog/cbctdes.v index 4eccdd6..4bddbf0 100644 --- a/cbctdes/rtl/verilog/cbctdes.v +++ b/cbctdes/rtl/verilog/cbctdes.v @@ -44,9 +44,9 @@ module cbctdes wire tdes_mode; reg start; reg [0:63] key; - wire [0:63] tdes_key1; - wire [0:63] tdes_key2; - wire [0:63] tdes_key3; + wire [0:63] tdes_key1; + wire [0:63] tdes_key2; + wire [0:63] tdes_key3; reg [0:63] key1; reg [0:63] key2; reg [0:63] key3; @@ -56,7 +56,6 @@ module cbctdes reg [0:63] tdes_datain; wire validin; wire [0:63] tdes_dataout; - reg reset; reg [0:63] dataout; wire tdes_ready; @@ -97,18 +96,16 @@ module cbctdes // input register always @(posedge clk_i, negedge reset_i) begin if (~reset_i) begin - reset <= 0; mode <= 0; start <= 0; - key1 <= 0; - key2 <= 0; - key3 <= 0; + key1 <= 0; + key2 <= 0; + key3 <= 0; iv <= 0; datain <= 0; datain_d <= 0; end else begin - reset <= reset_i; if (valid_i && ready_o) begin start <= start_i; datain <= data_i; @@ -128,14 +125,14 @@ module cbctdes // output register always @(posedge clk_i, negedge reset_i) begin if (~reset_i) begin - ready_o <= 0; + ready_o <= 1; dataout <= 0; end else begin if (valid_i && ready_o && tdes_ready) begin ready_o <= 0; end - else if (valid_o || (reset_i && ~reset)) begin + else if (valid_o) begin ready_o <= 1; dataout <= tdes_dataout; end @@ -145,7 +142,7 @@ module cbctdes // des instance tdes i_tdes ( - .reset_i(reset), + .reset_i(reset_i), .clk_i(clk_i), .mode_i(tdes_mode), .key1_i(tdes_key1), diff --git a/cbctdes/rtl/verilog/tdes.v b/cbctdes/rtl/verilog/tdes.v index b582b31..97bebf0 100644 --- a/cbctdes/rtl/verilog/tdes.v +++ b/cbctdes/rtl/verilog/tdes.v @@ -38,7 +38,6 @@ module tdes ); - reg reset; reg mode; reg [0:63] key1; reg [0:63] key2; @@ -65,14 +64,12 @@ module tdes // input register always @(posedge clk_i, negedge reset_i) begin if (~reset_i) begin - reset <= 0; mode <= 0; key1 <= 0; key2 <= 0; key3 <= 0; end else begin - reset <= reset_i; if (valid_i && ready_o) begin mode <= mode_i; key1 <= key1_i; @@ -86,13 +83,13 @@ module tdes // output register always @(posedge clk_i, negedge reset_i) begin if (~reset_i) begin - ready_o <= 0; + ready_o <= 1; end else begin if (valid_i && ready_o) begin ready_o <= 0; end - if (valid_o || (reset_i && ~reset)) begin + if (valid_o) begin ready_o <= 1; end end From de08e5315390dd9755d1c7d6f139918ed29f3b90 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Tue, 8 Jul 2014 01:34:00 +0200 Subject: [PATCH 5/6] removed internal synced copy of reset_i; set ready to high in reset --- cbctdes/rtl/vhdl/cbctdes.vhd | 15 ++++++--------- cbctdes/rtl/vhdl/tdes.vhd | 9 +++------ 2 files changed, 9 insertions(+), 15 deletions(-) diff --git a/cbctdes/rtl/vhdl/cbctdes.vhd b/cbctdes/rtl/vhdl/cbctdes.vhd index 3da1637..04f387b 100644 --- a/cbctdes/rtl/vhdl/cbctdes.vhd +++ b/cbctdes/rtl/vhdl/cbctdes.vhd @@ -62,7 +62,7 @@ architecture rtl of cbctdes is ready_o : out std_logic ); end component tdes; - + signal s_mode : std_logic; signal s_des_mode : std_logic; @@ -83,8 +83,7 @@ architecture rtl of cbctdes is signal s_validout : std_logic; signal s_ready : std_logic; signal s_readyout : std_logic; - signal s_reset : std_logic; - + begin @@ -107,7 +106,6 @@ begin inputregister : process(clk_i, reset_i) is begin if(reset_i = '0') then - s_reset <= '0'; s_mode <= '0'; s_start <= '0'; s_key1 <= (others => '0'); @@ -117,7 +115,6 @@ begin s_datain <= (others => '0'); s_datain_d <= (others => '0'); elsif(rising_edge(clk_i)) then - s_reset <= reset_i; if(valid_i = '1' and s_ready = '1') then s_start <= start_i; s_datain <= data_i; @@ -137,23 +134,23 @@ begin outputregister : process(clk_i, reset_i) is begin if(reset_i = '0') then - s_ready <= '0'; + s_ready <= '1'; s_dataout <= (others => '0'); elsif(rising_edge(clk_i)) then if(valid_i = '1' and s_ready = '1' and s_readyout = '1') then s_ready <= '0'; end if; - if(s_validout = '1' or (reset_i = '1' and s_reset = '0')) then + if(s_validout = '1') then s_ready <= '1'; s_dataout <= s_des_dataout; end if; end if; end process outputregister; - + i_tdes : tdes port map ( - reset_i => s_reset, + reset_i => reset_i, clk_i => clk_i, mode_i => s_des_mode, key1_i => s_tdes_key1, diff --git a/cbctdes/rtl/vhdl/tdes.vhd b/cbctdes/rtl/vhdl/tdes.vhd index d602f97..6dcda6a 100644 --- a/cbctdes/rtl/vhdl/tdes.vhd +++ b/cbctdes/rtl/vhdl/tdes.vhd @@ -60,7 +60,6 @@ architecture rtl of tdes is signal s_ready : std_logic; - signal s_reset : std_logic; signal s_mode : std_logic; signal s_des2_mode : std_logic; signal s_des1_validin : std_logic := '0'; @@ -90,13 +89,11 @@ begin inputregister : process(clk_i, reset_i) is begin if(reset_i = '0') then - s_reset <= '0'; s_mode <= '0'; s_key1 <= (others => '0'); s_key2 <= (others => '0'); s_key3 <= (others => '0'); elsif(rising_edge(clk_i)) then - s_reset <= reset_i; if(valid_i = '1' and s_ready = '1') then s_mode <= mode_i; s_key1 <= key1_i; @@ -105,17 +102,17 @@ begin end if; end if; end process inputregister; - + outputregister : process(clk_i, reset_i) is begin if(reset_i = '0') then - s_ready <= '0'; + s_ready <= '1'; elsif(rising_edge(clk_i)) then if(valid_i = '1' and s_ready = '1') then s_ready <= '0'; end if; - if(s_des3_validout = '1' or (reset_i = '1' and s_reset = '0')) then + if(s_des3_validout = '1') then s_ready <= '1'; end if; end if; From a83081760fa002d4215a58f229832e342ffe25ac Mon Sep 17 00:00:00 2001 From: tmeissner Date: Tue, 8 Jul 2014 01:34:54 +0200 Subject: [PATCH 6/6] added prototype of addroundkey() function --- aes/rtl/vhdl/aes_pkg.vhd | 2 ++ 1 file changed, 2 insertions(+) diff --git a/aes/rtl/vhdl/aes_pkg.vhd b/aes/rtl/vhdl/aes_pkg.vhd index 7afeadc..ed4baa6 100644 --- a/aes/rtl/vhdl/aes_pkg.vhd +++ b/aes/rtl/vhdl/aes_pkg.vhd @@ -85,6 +85,8 @@ package aes_pkg is function gmul (a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0)) return std_logic_vector; + function addroundkey (data : in std_logic_vector(127 downto 0), key ) + end package aes_pkg;