From 250fbf34b39db3ab3253531481c1f0f260fdf0b1 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Mon, 30 Nov 2020 19:08:48 +0100 Subject: [PATCH] Update CI-badge; add hint to VHPIdirect use in *aes testbenches --- README.md | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 9b0345e..8a9c324 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,4 @@ -

- 'simulation' workflow Status -

+[![simulation](https://img.shields.io/github/workflow/status/tmeissner/cryptocores/Simulation/master?longCache=true&style=flat-square&label=simulation&logo=Github%20Actions&logoColor=fff)](https://github.com/tmeissner/cryptocores/actions?query=workflow%3ASimulation) # cryptocores Cryptography IP-cores & tests written in VHDL / Verilog @@ -11,6 +8,10 @@ They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes. +The testbenches to verify [AES](aes/sim/vhdl/) and [CTR-AES](ctraes/sim/vhdl/) are examples +how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness +of the VHDL implementation. + *HINT:* The tests of some algorithms use the OSVVM library, which is redistributed as