From 2a2aa23e21c8cec43399a74c7c11618ca2dd9dd4 Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Tue, 8 Jul 2014 01:30:56 +0200
Subject: [PATCH] wait for rising edge of reset before send stimuli data

---
 cbctdes/sim/verilog/tb_cbctdes.v | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/cbctdes/sim/verilog/tb_cbctdes.v b/cbctdes/sim/verilog/tb_cbctdes.v
index 96b44c1..dbb2a74 100644
--- a/cbctdes/sim/verilog/tb_cbctdes.v
+++ b/cbctdes/sim/verilog/tb_cbctdes.v
@@ -89,6 +89,7 @@ module tb_cbctdes;
   initial
     forever @(negedge reset) begin
       index = 0;
+      wait (reset);
       while (index < 19) begin
         @(posedge clk)
           if (ready) begin
@@ -131,7 +132,7 @@ module tb_cbctdes;
   // checker process
   always begin : checker
 
-    wait (reset)
+    wait (reset);
 
     outdex = 0;
     // encryption tests