diff --git a/cbcmac_des/sim/verilog/data_input.txt b/cbcmac_des/sim/verilog/data_input.txt
new file mode 100644
index 0000000..ea0f2ac
--- /dev/null
+++ b/cbcmac_des/sim/verilog/data_input.txt
@@ -0,0 +1,4 @@
+3736353433323120
+4e6f772069732074
+68652074696d6520
+666f722000000000
\ No newline at end of file
diff --git a/cbcmac_des/sim/verilog/data_output.txt b/cbcmac_des/sim/verilog/data_output.txt
new file mode 100644
index 0000000..ca73ee5
--- /dev/null
+++ b/cbcmac_des/sim/verilog/data_output.txt
@@ -0,0 +1,4 @@
+21fb193693a16c28
+6c463f0cb7167a6f
+956ee891e889d91e
+f1d30f6849312ca4
\ No newline at end of file
diff --git a/cbcmac_des/sim/verilog/makefile b/cbcmac_des/sim/verilog/makefile
new file mode 100644
index 0000000..4f752f6
--- /dev/null
+++ b/cbcmac_des/sim/verilog/makefile
@@ -0,0 +1,43 @@
+# ======================================================================
+# DES encryption/decryption
+# algorithm according to FIPS 46-3 specification
+# Copyright (C) 2012 Torsten Meissner
+#-----------------------------------------------------------------------
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+# ======================================================================
+
+
+SRC_FILES = tb_cbcmac_des.v ../../rtl/verilog/cbcmac_des.v ../../../des/rtl/verilog/des.v
+SIM_FILES = data_input.txt data_output.txt
+
+.PHONY: all
+all : sim wave
+
+.PHONY: sim
+sim : tb_cbcmac_des.vcd
+
+tb_cbcmac_des.vcd : $(SRC_FILES) $(SIM_FILES)
+	iverilog -Wall -s tb_cbcmac_des -o tb_cbcmac_des $(SRC_FILES)
+	vvp tb_cbcmac_des
+
+.PHONY: wave
+wave : tb_cbcmac_des.vcd
+	gtkwave -S tb_cbcmac_des.tcl tb_cbcmac_des.vcd &
+
+.PHONY: clean
+clean :
+	echo "# cleaning simulation files"
+	rm -f tb_cbcmac_des
+	rm -f tb_cbcmac_des.vcd
diff --git a/cbcmac_des/sim/verilog/tb_cbcmac_des.tcl b/cbcmac_des/sim/verilog/tb_cbcmac_des.tcl
new file mode 100644
index 0000000..20781ea
--- /dev/null
+++ b/cbcmac_des/sim/verilog/tb_cbcmac_des.tcl
@@ -0,0 +1,12 @@
+set signals [list]
+lappend signals "tb_cbcmac_des.reset"
+lappend signals "tb_cbcmac_des.clk"
+lappend signals "tb_cbcmac_des.validin"
+lappend signals "tb_cbcmac_des.acceptout"
+lappend signals "tb_cbcmac_des.start"
+lappend signals "tb_cbcmac_des.key"
+lappend signals "tb_cbcmac_des.datain"
+lappend signals "tb_cbcmac_des.validout"
+lappend signals "tb_cbcmac_des.acceptin"
+lappend signals "tb_cbcmac_des.dataout"
+set num_added [ gtkwave::addSignalsFromList $signals ]
diff --git a/cbcmac_des/sim/verilog/tb_cbcmac_des.v b/cbcmac_des/sim/verilog/tb_cbcmac_des.v
new file mode 100644
index 0000000..895938d
--- /dev/null
+++ b/cbcmac_des/sim/verilog/tb_cbcmac_des.v
@@ -0,0 +1,154 @@
+// ======================================================================
+// DES encryption/decryption testbench
+// tests according to NIST 800-17 special publication
+// Copyright (C) 2012 Torsten Meissner
+//-----------------------------------------------------------------------
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+// ======================================================================
+
+`timescale 1ns/1ps
+
+
+module tb_cbcmac_des;
+
+
+  // set dumpfile
+  initial begin
+    $dumpfile ("tb_cbcmac_des.vcd");
+    $dumpvars (0, tb_cbcmac_des);
+  end
+
+
+  reg reset;
+  reg clk = 0;
+  reg start;
+  reg [0:63] key;
+  reg [0:63] datain;
+  reg validin;
+  reg acceptin;
+  integer index;
+  integer outdex;
+  integer errors;
+  wire [0:63] dataout;
+  wire validout;
+  wire acceptout;
+
+  reg [0:63] data_input  [0:3];
+  reg [0:63] key_input = 64'h0123456789abcdef;
+  reg [0:63] data_output [0:3];
+
+  // read in test data files
+  initial begin
+    $readmemh("data_input.txt",  data_input);
+    $readmemh("data_output.txt", data_output);
+  end
+
+
+  // setup simulation
+  initial begin
+    reset = 1;
+    #1  reset = 0;
+    #20 reset = 1;
+  end
+
+
+  // generate clock with 100 mhz
+  always #5 clk = !clk;
+
+
+  // init the register values
+  initial
+    forever @(negedge reset) begin
+      //disable stimuli;
+      disable checker;
+      start   <= 0;
+      validin <= 0;
+      key     <= 0;
+      datain  <= 0;
+      errors   = 0;
+    end
+
+
+   // stimuli generator process
+  initial
+    forever @(posedge reset) begin
+      @(posedge clk)
+        for (index = 0; index < 4; index = index + 1)
+        begin
+          @(posedge acceptout)
+            validin <= 1;
+            datain  <= data_input[index];
+            if (index == 0) begin
+              key   <= key_input;
+              start <= 1;
+            end
+          @(negedge acceptout)
+            validin <= 0;
+            start   <= 0;
+            key     <= 0;
+        end
+    end
+
+
+  // checker process
+  always begin : checker
+
+    wait (reset)
+
+    acceptin <= 1;
+
+    // encryption tests
+    @(posedge clk)
+    for(outdex = 0; outdex < 4; outdex = outdex + 1)
+    begin
+      @(posedge validout)
+      // detected an error -> print error message
+      // increment error counter
+      if (dataout != data_output[outdex]) begin
+        $display ("error, output was %h - should have been %h", dataout, data_output[outdex]);
+        errors = errors + 1;
+      end
+    end
+
+    // simulation finished -> print messages and if an error was detected
+    $display   ("#############");
+    if (errors) begin
+      $display ("Tests finished, %0d errors detected :(", errors);
+    end else begin
+      $display ("Tests finished, no errors detected :)");
+    end
+    $display ("#############");
+
+    @(posedge clk)
+      $finish;
+  end
+
+
+  // dut
+  cbcmac_des i_cbcmac_des (
+    .reset_i(reset),
+    .clk_i(clk),
+    .start_i(start),
+    .key_i(key),
+    .data_i(datain),
+    .valid_i(validin),
+    .accept_o(acceptout),
+    .data_o(dataout),
+    .valid_o(validout),
+    .accept_i(acceptin)
+  );
+
+
+endmodule