From 325a08f3013c5fabacb27b56ab175db0d2005318 Mon Sep 17 00:00:00 2001
From: umarcor <unai.martinezcorral@ehu.eus>
Date: Fri, 27 Nov 2020 03:24:17 +0100
Subject: [PATCH] aes: fix VHDL sources order

---
 aes/sim/vhdl/Makefile | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/aes/sim/vhdl/Makefile b/aes/sim/vhdl/Makefile
index 0ce8dc9..99d93b7 100644
--- a/aes/sim/vhdl/Makefile
+++ b/aes/sim/vhdl/Makefile
@@ -20,9 +20,10 @@
 
 RTL_SRC := \
   ../../rtl/vhdl/aes_pkg.vhd \
-  ../../rtl/vhdl/aes.vhd     \
   ../../rtl/vhdl/aes_enc.vhd \
-  ../../rtl/vhdl/aes_dec.vhd
+  ../../rtl/vhdl/aes_dec.vhd \
+  ../../rtl/vhdl/aes.vhd
+
 
 SIM_SRC   := tb_aes.vhd
 C_SRC     := tb_aes.c