From 3531c69ce16b8cf0487da9893658b6fa17b65589 Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Wed, 25 Mar 2015 22:56:49 +0100
Subject: [PATCH] add support for ITER & PIPE variations of DES verilog
 implementation

---
 des/sim/verilog/makefile | 30 ++++++++++++++++-------
 des/sim/verilog/tb_des.v | 52 +++++++++++++++++++++++++++++++++++-----
 2 files changed, 67 insertions(+), 15 deletions(-)

diff --git a/des/sim/verilog/makefile b/des/sim/verilog/makefile
index 08e9b4d..1425e03 100644
--- a/des/sim/verilog/makefile
+++ b/des/sim/verilog/makefile
@@ -22,20 +22,32 @@
 SRC_FILES = ../../rtl/verilog/*.v tb_des.v
 SIM_FILES = data_input.txt key_input.txt data_output.txt
 
+.PHONY: all
+all : sim_pipe sim_iter
 
-all : sim wave
+.PHONY: sim_pipe
+sim_pipe : tb_des_pipe.vcd
 
-sim : tb_des.vcd
+.PHONY: sim_iter
+sim_iter : tb_des_iter.vcd
 
+tb_des_pipe.vcd : $(SRC_FILES) $(SIM_FILES)
+	iverilog -Wall -DPIPE -s tb_des -o tb_des_pipe tb_des.v ../../rtl/verilog/des.v
+	vvp tb_des_pipe
 
-tb_des.vcd : $(SRC_FILES) $(SIM_FILES)
-	iverilog -Wall -s tb_des -o tb_des tb_des.v ../../rtl/verilog/des.v
-	vvp tb_des
+tb_des_iter.vcd : $(SRC_FILES) $(SIM_FILES)
+	iverilog -Wall -DITER -s tb_des -o tb_des_iter tb_des.v ../../rtl/verilog/des.v
+	vvp tb_des_iter
+
+.PHONY: wave_pipe
+wave_pipe : tb_des_pipe.vcd
+	gtkwave -S tb_des.tcl tb_des_pipe.vcd &
+
+.PHONY: wave_iter
+wave_iter : tb_des_iter.vcd
+	gtkwave -S tb_des.tcl tb_des_iter.vcd &
 
-wave : tb_des.vcd
-	gtkwave -T tb_des.tcl tb_des.vcd
-	
 clean :
 	echo "# cleaning simulation files"
-	rm -f tb_des
+	rm -f tb_des_*
 	rm -f tb_des.vcd
diff --git a/des/sim/verilog/tb_des.v b/des/sim/verilog/tb_des.v
index 6805fa9..f2f16bc 100644
--- a/des/sim/verilog/tb_des.v
+++ b/des/sim/verilog/tb_des.v
@@ -21,14 +21,17 @@
 `timescale 1ns/1ps
 
 
-
 module tb_des;
 
 
   // set dumpfile
   initial begin
-     $dumpfile ("tb_des.vcd");
-     $dumpvars (0, tb_des);
+`ifdef ITER
+    $dumpfile ("tb_des_iter.vcd");
+`else
+    $dumpfile ("tb_des_pipe.vcd");
+`endif
+    $dumpvars (0, tb_des);
   end
 
 
@@ -38,18 +41,19 @@ module tb_des;
   reg [0:63] key;
   reg [0:63] datain;
   reg validin;
+  reg acceptin;
   integer index;
   integer outdex;
   integer enc_errors;
   integer dec_errors;
   wire [0:63] dataout;
   wire validout;
+  wire acceptout;
 
   reg [0:63] data_input  [0:469];
   reg [0:63] key_input   [0:469];
   reg [0:63] data_output [0:469];
 
-
   // read in test data files
   initial begin
     $readmemh("data_input.txt",  data_input);
@@ -86,15 +90,23 @@ module tb_des;
 
    // stimuli generator process
   initial
-    forever @(negedge reset) begin
+    forever @(posedge reset) begin
       @(posedge clk)
         for (index = 0; index < 235; index = index + 1)
         begin
+`ifdef ITER
+          @(posedge acceptout)
+`else
           @(posedge clk)
+`endif
             mode    <= 0;
             validin <= 1;
             datain  <= data_input[index];
             key     <= key_input[index];
+`ifdef ITER
+          @(negedge acceptout)
+            validin <= 0;
+`endif
         end
         for (index = 0; index < 10; index = index + 1)
         begin
@@ -103,11 +115,19 @@ module tb_des;
         end
         for (index = 235; index < 470; index = index + 1)
         begin
+`ifdef ITER
+          @(posedge acceptout)
+`else
           @(posedge clk)
+`endif
             mode    <= 1;
             validin <= 1;
             datain  <= data_input[index];
             key     <= key_input[index];
+`ifdef ITER
+          @(negedge acceptout)
+            validin <= 0;
+`endif
         end
         @(posedge clk)
           validin <= 0;
@@ -120,11 +140,21 @@ module tb_des;
 
     wait (reset)
 
+    acceptin <= 1;
+
     // encryption tests
+`ifdef ITER
+    @(posedge clk)
+`else
     @(posedge validout)
+`endif
     for(outdex = 0; outdex < 235; outdex = outdex + 1)
     begin
+`ifdef ITER
+      @(posedge validout)
+`else
       @(posedge clk)
+`endif
       // detected an error -> print error message
       // increment error counter
       if (dataout != data_output[outdex]) begin
@@ -142,10 +172,18 @@ module tb_des;
     end
 
     // decryption tests
+`ifdef ITER
+    @(posedge clk)
+`else
     @(posedge validout)
+`endif
     for(outdex = 235; outdex < 470; outdex = outdex + 1)
     begin
+`ifdef ITER
+      @(posedge validout)
+`else
       @(posedge clk)
+`endif
       // detected an error -> print error message
       // increment error counter
        if (dataout != data_output[outdex]) begin
@@ -183,8 +221,10 @@ module tb_des;
     .key_i(key),
     .data_i(datain),
     .valid_i(validin),
+    .accept_o(acceptout),
     .data_o(dataout),
-    .valid_o(validout)
+    .valid_o(validout),
+    .accept_i(acceptin)
   );