From 42d69ab72f9ce41c8c874781066d3109efb2f780 Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Sat, 22 Oct 2011 00:33:49 +0200 Subject: [PATCH] Initial release, pre-alpha state, only framework code --- aes/rtl/aes.vhd | 52 ++++++++++++++++++++++++++++ aes/rtl/aes_pkg.vhd | 60 +++++++++++++++++++++++++++++++++ aes/sim/makefile | 41 +++++++++++++++++++++++ aes/sim/tb_aes.vhd | 82 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 235 insertions(+) create mode 100644 aes/rtl/aes.vhd create mode 100644 aes/rtl/aes_pkg.vhd create mode 100644 aes/sim/makefile create mode 100644 aes/sim/tb_aes.vhd diff --git a/aes/rtl/aes.vhd b/aes/rtl/aes.vhd new file mode 100644 index 0000000..c1e52c6 --- /dev/null +++ b/aes/rtl/aes.vhd @@ -0,0 +1,52 @@ +-- ====================================================================== +-- AES encryption/decryption +-- algorithm according to FIPS 197 specification +-- Copyright (C) 2011 Torsten Meissner +------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- ====================================================================== + + +-- Revision 0.1 2011/10/22 +-- Initial release + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.aes_pkg.all; + + +entity aes is + port ( + reset_i : in std_logic; -- async reset + clk_i : in std_logic; -- clock + mode_i : in std_logic; -- aes-modus: 0 = encrypt, 1 = decrypt + key_i : in std_logic_vector(0 TO 127); -- key input + data_i : in std_logic_vector(0 TO 127); -- data input + valid_i : in std_logic; -- input key/data valid flag + data_o : out std_logic_vector(0 TO 127); -- data output + valid_o : out std_logic -- output data valid flag + ); +end entity aes; + + +architecture rtl of aes is + + +begin + + +end architecture rtl; diff --git a/aes/rtl/aes_pkg.vhd b/aes/rtl/aes_pkg.vhd new file mode 100644 index 0000000..bda47c7 --- /dev/null +++ b/aes/rtl/aes_pkg.vhd @@ -0,0 +1,60 @@ +-- ====================================================================== +-- AES encryption/decryption +-- package file with functions +-- Copyright (C) 2011 Torsten Meissner +------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- ====================================================================== + + +-- Revision 0.1 2011/10/22 +-- Initial release + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +package aes_pkg is + + FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; + +end package aes_pkg; + + +package body aes_pkg is + + FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63; + VARIABLE table : matrix := (57, 49, 41, 33, 25, 17, 9, 1, + 59, 51, 43, 35, 27, 19, 11, 3, + 61, 53, 45, 37, 29, 21, 13, 5, + 63, 55, 47, 39, 31, 23, 15, 7, + 56, 48, 40, 32, 24, 16, 8, 0, + 58, 50, 42, 34, 26, 18, 10, 2, + 60, 52, 44, 36, 28, 20, 12, 4, + 62, 54, 46, 38, 30, 22, 14, 6); + VARIABLE result : std_logic_vector(0 TO 63); + BEGIN + FOR index IN 0 TO 63 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION ip; + + +end package body aes_pkg; diff --git a/aes/sim/makefile b/aes/sim/makefile new file mode 100644 index 0000000..3955e32 --- /dev/null +++ b/aes/sim/makefile @@ -0,0 +1,41 @@ +# ====================================================================== +# AES encryption/decryption +# algorithm according to FIPS 197 specification +# Copyright (C) 2011 Torsten Meissner +#----------------------------------------------------------------------- +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# ====================================================================== + + +# Revision 0.1 2011/10/22 +# Initial release + + +all : sim wave + +sim : tb_aes.ghw + +tb_aes.ghw : ../rtl/*.vhd tb_aes.vhd + ghdl -a ../rtl/aes_pkg.vhd ../rtl/aes.vhd tb_aes.vhd + ghdl -e tb_aes + ghdl -r tb_aes --wave=tb_aes.ghw --assert-level=error --stop-time=10us + +wave : tb_aes.ghw + gtkwave tb_aes.ghw + +clean : + echo "# cleaning simulation files" + rm -f tb_aes.ghw + rm -f work*.cf diff --git a/aes/sim/tb_aes.vhd b/aes/sim/tb_aes.vhd new file mode 100644 index 0000000..b813eff --- /dev/null +++ b/aes/sim/tb_aes.vhd @@ -0,0 +1,82 @@ +-- ====================================================================== +-- AES encryption/decryption testbench +-- tests according to NIST special publication +-- Copyright (C) 2011 Torsten Meissner +------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- ====================================================================== + + +-- Revision 0.1 2011/10/22 +-- Initial release + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity tb_aes is +end entity tb_aes; + + +architecture rtl of tb_aes is + + + signal s_reset : std_logic := '0'; + signal s_clk : std_logic := '0'; + signal s_mode : std_logic := '0'; + signal s_key : std_logic_vector(0 to 127) := (others => '0'); + signal s_datain : std_logic_vector(0 to 127) := (others => '0'); + signal s_validin : std_logic := '0'; + signal s_dataout : std_logic_vector(0 to 127); + signal s_validout : std_logic; + + + component aes is + port ( + reset_i : in std_logic; + clk_i : in std_logic; + mode_i : in std_logic; + key_i : in std_logic_vector(0 TO 127); + data_i : in std_logic_vector(0 TO 127); + valid_i : in std_logic; + data_o : out std_logic_vector(0 TO 127); + valid_o : out std_logic + ); + end component aes; + + +begin + + + s_clk <= not(s_clk) after 10 ns; + s_reset <= '1' after 100 ns; + + + i_aes : aes + port map ( + reset_i => s_reset, + clk_i => s_clk, + mode_i => s_mode, + key_i => s_key, + data_i => s_datain, + valid_i => s_validin, + data_o => s_dataout, + valid_o => s_validout + ); + + +end architecture rtl;