From 4b8ab0d0cc7385fea6428c9ea2a586f64933df51 Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Sat, 15 Oct 2011 17:49:58 +0200 Subject: [PATCH] added async reset to des-module to avoid simulation warnings and unititialized ports --- cbcdes/rtl/cbcdes.vhd | 2 ++ cbcdes/rtl/des.vhd | 6 +++++- des/rtl/des.vhd | 6 +++++- des/sim/tb_des.vhd | 8 ++++++-- tdes/rtl/des.vhd | 6 +++++- tdes/rtl/tdes.vhd | 4 ++++ 6 files changed, 27 insertions(+), 5 deletions(-) diff --git a/cbcdes/rtl/cbcdes.vhd b/cbcdes/rtl/cbcdes.vhd index 86c11ae..518a4f1 100644 --- a/cbcdes/rtl/cbcdes.vhd +++ b/cbcdes/rtl/cbcdes.vhd @@ -53,6 +53,7 @@ architecture rtl of cbcdes is component des is port ( + reset_i : in std_logic; clk_i : IN std_logic; -- clock mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt key_i : IN std_logic_vector(0 TO 63); -- key input @@ -142,6 +143,7 @@ begin i_des : des port map ( + reset_i => s_reset, clk_i => clk_i, mode_i => s_des_mode, key_i => s_des_key, diff --git a/cbcdes/rtl/des.vhd b/cbcdes/rtl/des.vhd index ad7bbdd..9ebc905 100644 --- a/cbcdes/rtl/des.vhd +++ b/cbcdes/rtl/des.vhd @@ -33,6 +33,7 @@ USE work.des_pkg.ALL; ENTITY des IS PORT ( + reset_i : in std_logic; -- async reset clk_i : IN std_logic; -- clock mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt key_i : IN std_logic_vector(0 TO 63); -- key input @@ -140,7 +141,10 @@ BEGIN VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0'); VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0'); BEGIN - IF rising_edge( clk_i ) THEN + if(reset_i = '0') then + data_o <= (others => '0'); + valid_o <= '0'; + elsif rising_edge( clk_i ) THEN -- shift registers valid(1 TO 17) := valid(0 TO 16); valid(0) := valid_i; diff --git a/des/rtl/des.vhd b/des/rtl/des.vhd index ad7bbdd..9ebc905 100644 --- a/des/rtl/des.vhd +++ b/des/rtl/des.vhd @@ -33,6 +33,7 @@ USE work.des_pkg.ALL; ENTITY des IS PORT ( + reset_i : in std_logic; -- async reset clk_i : IN std_logic; -- clock mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt key_i : IN std_logic_vector(0 TO 63); -- key input @@ -140,7 +141,10 @@ BEGIN VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0'); VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0'); BEGIN - IF rising_edge( clk_i ) THEN + if(reset_i = '0') then + data_o <= (others => '0'); + valid_o <= '0'; + elsif rising_edge( clk_i ) THEN -- shift registers valid(1 TO 17) := valid(0 TO 16); valid(0) := valid_i; diff --git a/des/sim/tb_des.vhd b/des/sim/tb_des.vhd index 9a7fbdb..9012035 100644 --- a/des/sim/tb_des.vhd +++ b/des/sim/tb_des.vhd @@ -141,6 +141,7 @@ architecture rtl of tb_des is x"2F22E49BAB7CA1AC", x"5A6B612CC26CCE4A", x"5F4C038ED12B2E41", x"63FAC0D034D9F793"); + signal s_reset : std_logic := '0'; signal s_clk : std_logic := '0'; signal s_mode : std_logic := '0'; signal s_key : std_logic_vector(0 to 63) := (others => '0'); @@ -152,6 +153,7 @@ architecture rtl of tb_des is component des is port ( + reset_i : in std_logic; clk_i : in std_logic; mode_i : in std_logic; key_i : in std_logic_vector(0 TO 63); @@ -166,8 +168,8 @@ architecture rtl of tb_des is begin - s_clk <= not(s_clk) after 10 ns; - + s_clk <= not(s_clk) after 10 ns; + s_reset <= '1' after 100 ns; teststimuliP : process is begin @@ -176,6 +178,7 @@ begin s_validin <= '0'; s_key <= x"0101010101010101"; s_datain <= x"8000000000000000"; + wait until s_reset = '1'; -- Variable plaintext known answer test for index in c_variable_plaintext_known_answers'range loop wait until rising_edge(s_clk); @@ -418,6 +421,7 @@ begin i_des : des port map ( + reset_i => s_reset, clk_i => s_clk, mode_i => s_mode, key_i => s_key, diff --git a/tdes/rtl/des.vhd b/tdes/rtl/des.vhd index ad7bbdd..9ebc905 100644 --- a/tdes/rtl/des.vhd +++ b/tdes/rtl/des.vhd @@ -33,6 +33,7 @@ USE work.des_pkg.ALL; ENTITY des IS PORT ( + reset_i : in std_logic; -- async reset clk_i : IN std_logic; -- clock mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt key_i : IN std_logic_vector(0 TO 63); -- key input @@ -140,7 +141,10 @@ BEGIN VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0'); VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0'); BEGIN - IF rising_edge( clk_i ) THEN + if(reset_i = '0') then + data_o <= (others => '0'); + valid_o <= '0'; + elsif rising_edge( clk_i ) THEN -- shift registers valid(1 TO 17) := valid(0 TO 16); valid(0) := valid_i; diff --git a/tdes/rtl/tdes.vhd b/tdes/rtl/tdes.vhd index 0ab9f9c..087aa4c 100644 --- a/tdes/rtl/tdes.vhd +++ b/tdes/rtl/tdes.vhd @@ -51,6 +51,7 @@ architecture rtl of tdes is component des is port ( + reset_i : in std_logic; clk_i : IN std_logic; -- clock mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt key_i : IN std_logic_vector(0 TO 63); -- key input @@ -127,6 +128,7 @@ begin i1_des : des port map ( + reset_i => reset_i, clk_i => clk_i, mode_i => mode_i, key_i => s_des1_key, @@ -139,6 +141,7 @@ begin i2_des : des port map ( + reset_i => reset_i, clk_i => clk_i, mode_i => s_des2_mode, key_i => s_key2, @@ -151,6 +154,7 @@ begin i3_des : des port map ( + reset_i => reset_i, clk_i => clk_i, mode_i => s_mode, key_i => s_des3_key,