diff --git a/des/sim/verilog/makefile b/des/sim/verilog/makefile
index 1425e03..411f8a1 100644
--- a/des/sim/verilog/makefile
+++ b/des/sim/verilog/makefile
@@ -47,6 +47,7 @@ wave_pipe : tb_des_pipe.vcd
 wave_iter : tb_des_iter.vcd
 	gtkwave -S tb_des.tcl tb_des_iter.vcd &
 
+.PHONY: clean
 clean :
 	echo "# cleaning simulation files"
 	rm -f tb_des_*