From 7822728a748a494a12588af2c9d9d8d40207a067 Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Sun, 24 Mar 2013 15:58:51 +0100 Subject: [PATCH 1/8] moved into seperate vhdl folder --- tdes/rtl/des.vhd | 340 ------------------------------------------- tdes/rtl/des_pkg.vhd | 333 ------------------------------------------ tdes/rtl/tdes.vhd | 168 --------------------- 3 files changed, 841 deletions(-) delete mode 100644 tdes/rtl/des.vhd delete mode 100644 tdes/rtl/des_pkg.vhd delete mode 100644 tdes/rtl/tdes.vhd diff --git a/tdes/rtl/des.vhd b/tdes/rtl/des.vhd deleted file mode 100644 index 9ebc905..0000000 --- a/tdes/rtl/des.vhd +++ /dev/null @@ -1,340 +0,0 @@ --- ====================================================================== --- DES encryption/decryption --- algorithm according to FIPS 46-3 specification --- Copyright (C) 2007 Torsten Meissner -------------------------------------------------------------------------- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. - --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. - --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA --- ====================================================================== - - --- Revision 1.0 2007/02/04 --- Initial release --- Revision 1.1 2007/02/05 --- Corrected error in use of mode register for key calculation - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.numeric_std.ALL; -USE work.des_pkg.ALL; - - -ENTITY des IS - PORT ( - reset_i : in std_logic; -- async reset - clk_i : IN std_logic; -- clock - mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt - key_i : IN std_logic_vector(0 TO 63); -- key input - data_i : IN std_logic_vector(0 TO 63); -- data input - valid_i : IN std_logic; -- input key/data valid flag - data_o : OUT std_logic_vector(0 TO 63); -- data output - valid_o : OUT std_logic -- output data valid flag - ); -END ENTITY des; - - -ARCHITECTURE rtl OF des IS - -BEGIN - - crypt : PROCESS ( clk_i ) IS - -- variables for key calculation - VARIABLE c0 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c1 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c2 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c3 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c4 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c5 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c6 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c7 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c8 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c9 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d0 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d1 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d2 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d3 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d4 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d5 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d6 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d7 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d8 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d9 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0'); - -- key variables - VARIABLE key1 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key2 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key3 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key4 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key5 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key6 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key7 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key8 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key9 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0'); - -- variables for left & right data blocks - VARIABLE l0 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l1 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l2 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l3 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l4 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l5 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l6 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l7 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l8 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l9 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r0 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r1 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r2 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r3 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r4 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r5 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r6 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r7 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r8 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r9 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0'); - -- variables for mode & valid shift registers - VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0'); - VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0'); - BEGIN - if(reset_i = '0') then - data_o <= (others => '0'); - valid_o <= '0'; - elsif rising_edge( clk_i ) THEN - -- shift registers - valid(1 TO 17) := valid(0 TO 16); - valid(0) := valid_i; - mode(1 TO 16) := mode(0 TO 15); - mode(0) := mode_i; - -- output stage - valid_o <= valid(17); - data_o <= ipn( ( r16 & l16 ) ); - -- 16. stage - IF mode(16) = '0' THEN - c16 := c15(1 TO 27) & c15(0); - d16 := d15(1 TO 27) & d15(0); - ELSE - c16 := c15(27) & c15(0 TO 26); - d16 := d15(27) & d15(0 TO 26); - END IF; - key16 := pc2( ( c16 & d16 ) ); - l16 := r15; - r16 := l15 xor ( f( r15, key16 ) ); - -- 15. stage - IF mode(15) = '0' THEN - c15 := c14(2 TO 27) & c14(0 TO 1); - d15 := d14(2 TO 27) & d14(0 TO 1); - ELSE - c15 := c14(26 TO 27) & c14(0 TO 25); - d15 := d14(26 TO 27) & d14(0 TO 25); - END IF; - key15 := pc2( ( c15 & d15 ) ); - l15 := r14; - r15 := l14 xor ( f( r14, key15 ) ); - -- 14. stage - IF mode(14) = '0' THEN - c14 := c13(2 TO 27) & c13(0 TO 1); - d14 := d13(2 TO 27) & d13(0 TO 1); - ELSE - c14 := c13(26 TO 27) & c13(0 TO 25); - d14 := d13(26 TO 27) & d13(0 TO 25); - END IF; - key14 := pc2( ( c14 & d14 ) ); - l14 := r13; - r14 := l13 xor ( f( r13, key14 ) ); - -- 13. stage - IF mode(13) = '0' THEN - c13 := c12(2 TO 27) & c12(0 TO 1); - d13 := d12(2 TO 27) & d12(0 TO 1); - ELSE - c13 := c12(26 TO 27) & c12(0 TO 25); - d13 := d12(26 TO 27) & d12(0 TO 25); - END IF; - key13 := pc2( ( c13 & d13 ) ); - l13 := r12; - r13 := l12 xor ( f( r12, key13 ) ); - -- 12. stage - IF mode(12) = '0' THEN - c12 := c11(2 TO 27) & c11(0 TO 1); - d12 := d11(2 TO 27) & d11(0 TO 1); - ELSE - c12 := c11(26 TO 27) & c11(0 TO 25); - d12 := d11(26 TO 27) & d11(0 TO 25); - END IF; - key12 := pc2( ( c12 & d12 ) ); - l12 := r11; - r12 := l11 xor ( f( r11, key12 ) ); - -- 11. stage - IF mode(11) = '0' THEN - c11 := c10(2 TO 27) & c10(0 TO 1); - d11 := d10(2 TO 27) & d10(0 TO 1); - ELSE - c11 := c10(26 TO 27) & c10(0 TO 25); - d11 := d10(26 TO 27) & d10(0 TO 25); - END IF; - key11 := pc2( ( c11 & d11 ) ); - l11 := r10; - r11 := l10 xor ( f( r10, key11 ) ); - -- 10. stage - IF mode(10) = '0' THEN - c10 := c9(2 TO 27) & c9(0 TO 1); - d10 := d9(2 TO 27) & d9(0 TO 1); - ELSE - c10 := c9(26 TO 27) & c9(0 TO 25); - d10 := d9(26 TO 27) & d9(0 TO 25); - END IF; - key10 := pc2( ( c10 & d10 ) ); - l10 := r9; - r10 := l9 xor ( f( r9, key10 ) ); - -- 9. stage - IF mode(9) = '0' THEN - c9 := c8(1 TO 27) & c8(0); - d9 := d8(1 TO 27) & d8(0); - ELSE - c9 := c8(27) & c8(0 TO 26); - d9 := d8(27) & d8(0 TO 26); - END IF; - key9 := pc2( ( c9 & d9 ) ); - l9 := r8; - r9 := l8 xor ( f( r8, key9 ) ); - -- 8. stage - IF mode(8) = '0' THEN - c8 := c7(2 TO 27) & c7(0 TO 1); - d8 := d7(2 TO 27) & d7(0 TO 1); - ELSE - c8 := c7(26 TO 27) & c7(0 TO 25); - d8 := d7(26 TO 27) & d7(0 TO 25); - END IF; - key8 := pc2( ( c8 & d8 ) ); - l8 := r7; - r8 := l7 xor ( f( r7, key8 ) ); - -- 7. stage - IF mode(7) = '0' THEN - c7 := c6(2 TO 27) & c6(0 TO 1); - d7 := d6(2 TO 27) & d6(0 TO 1); - ELSE - c7 := c6(26 TO 27) & c6(0 TO 25); - d7 := d6(26 TO 27) & d6(0 TO 25); - END IF; - key7 := pc2( ( c7 & d7 ) ); - l7 := r6; - r7 := l6 xor ( f( r6, key7 ) ); - -- 6. stage - IF mode(6) = '0' THEN - c6 := c5(2 TO 27) & c5(0 TO 1); - d6 := d5(2 TO 27) & d5(0 TO 1); - ELSE - c6 := c5(26 TO 27) & c5(0 TO 25); - d6 := d5(26 TO 27) & d5(0 TO 25); - END IF; - key6 := pc2( ( c6 & d6 ) ); - l6 := r5; - r6 := l5 xor ( f( r5, key6 ) ); - -- 5. stage - IF mode(5) = '0' THEN - c5 := c4(2 TO 27) & c4(0 TO 1); - d5 := d4(2 TO 27) & d4(0 TO 1); - ELSE - c5 := c4(26 TO 27) & c4(0 TO 25); - d5 := d4(26 TO 27) & d4(0 TO 25); - END IF; - key5 := pc2( ( c5 & d5 ) ); - l5 := r4; - r5 := l4 xor ( f( r4, key5 ) ); - -- 4. stage - IF mode(4) = '0' THEN - c4 := c3(2 TO 27) & c3(0 TO 1); - d4 := d3(2 TO 27) & d3(0 TO 1); - ELSE - c4 := c3(26 TO 27) & c3(0 TO 25); - d4 := d3(26 TO 27) & d3(0 TO 25); - END IF; - key4 := pc2( ( c4 & d4 ) ); - l4 := r3; - r4 := l3 xor ( f( r3, key4 ) ); - -- 3. stage - IF mode(3) = '0' THEN - c3 := c2(2 TO 27) & c2(0 TO 1); - d3 := d2(2 TO 27) & d2(0 TO 1); - ELSE - c3 := c2(26 TO 27) & c2(0 TO 25); - d3 := d2(26 TO 27) & d2(0 TO 25); - END IF; - key3 := pc2( ( c3 & d3 ) ); - l3 := r2; - r3 := l2 xor ( f( r2, key3 ) ); - -- 2. stage - IF mode(2) = '0' THEN - c2 := c1(1 TO 27) & c1(0); - d2 := d1(1 TO 27) & d1(0); - ELSE - c2 := c1(27) & c1(0 TO 26); - d2 := d1(27) & d1(0 TO 26); - END IF; - key2 := pc2( ( c2 & d2 ) ); - l2 := r1; - r2 := l1 xor ( f( r1, key2 ) ); - -- 1. stage - IF mode(1) = '0' THEN - c1 := c0(1 TO 27) & c0(0); - d1 := d0(1 TO 27) & d0(0); - ELSE - c1 := c0; - d1 := d0; - END IF; - key1 := pc2( ( c1 & d1 ) ); - l1 := r0; - r1 := l0 xor ( f( r0, key1 ) ); - -- input stage - l0 := ip( data_i )(0 TO 31); - r0 := ip( data_i )(32 TO 63); - c0 := pc1_c( key_i ); - d0 := pc1_d( key_i ); - END IF; - END PROCESS crypt; - -END ARCHITECTURE rtl; diff --git a/tdes/rtl/des_pkg.vhd b/tdes/rtl/des_pkg.vhd deleted file mode 100644 index 384209e..0000000 --- a/tdes/rtl/des_pkg.vhd +++ /dev/null @@ -1,333 +0,0 @@ --- ====================================================================== --- DES encryption/decryption --- package file with functions --- Copyright (C) 2007 Torsten Meissner -------------------------------------------------------------------------- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. - --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. - --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA --- ====================================================================== - - --- Revision 1.0 2007/02/04 --- Initial release - - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.numeric_std.ALL; - - -PACKAGE des_pkg IS - - FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - - FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; - FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; - - FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - - FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector; - - FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector; - -END PACKAGE des_pkg; - - -PACKAGE BODY des_pkg IS - - FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63; - VARIABLE table : matrix := (57, 49, 41, 33, 25, 17, 9, 1, - 59, 51, 43, 35, 27, 19, 11, 3, - 61, 53, 45, 37, 29, 21, 13, 5, - 63, 55, 47, 39, 31, 23, 15, 7, - 56, 48, 40, 32, 24, 16, 8, 0, - 58, 50, 42, 34, 26, 18, 10, 2, - 60, 52, 44, 36, 28, 20, 12, 4, - 62, 54, 46, 38, 30, 22, 14, 6); - VARIABLE result : std_logic_vector(0 TO 63); - BEGIN - FOR index IN 0 TO 63 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION ip; - - FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63; - VARIABLE table : matrix := (39, 7, 47, 15, 55, 23, 63, 31, - 38, 6, 46, 14, 54, 22, 62, 30, - 37, 5, 45, 13, 53, 21, 61, 29, - 36, 4, 44, 12, 52, 20, 60, 28, - 35, 3, 43, 11, 51, 19, 59, 27, - 34, 2, 42, 10, 50, 18, 58, 26, - 33, 1, 41, 9, 49, 17, 57, 25, - 32, 0, 40, 8, 48, 16, 56, 24); - VARIABLE result : std_logic_vector(0 TO 63); - BEGIN - FOR index IN 0 TO 63 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION ipn; - - FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31; - VARIABLE table : matrix := (31, 0, 1, 2, 3, 4, - 3, 4, 5, 6, 7, 8, - 7, 8, 9, 10, 11, 12, - 11, 12, 13, 14, 15, 16, - 15, 16, 17, 18, 19, 20, - 19, 20, 21, 22, 23, 24, - 23, 24, 25, 26, 27, 28, - 27, 28, 29, 30, 31, 0); - VARIABLE result : std_logic_vector(0 TO 47); - BEGIN - FOR index IN 0 TO 47 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION e; - - FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => (14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7), - 1 => ( 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8), - 2 => ( 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0), - 3 => (15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s1; - - FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => (15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10), - 1 => ( 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5), - 2 => ( 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15), - 3 => (13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s2; - - FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => (10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8), - 1 => (13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1), - 2 => (13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7), - 3 => ( 1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s3; - - FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => ( 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15), - 1 => (13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9), - 2 => (10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4), - 3 => ( 3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s4; - - FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => ( 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9), - 1 => (14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6), - 2 => ( 4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14), - 3 => (11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s5; - - FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => (12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11), - 1 => (10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8), - 2 => ( 9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6), - 3 => ( 4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s6; - - FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => ( 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1), - 1 => (13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6), - 2 => ( 1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2), - 3 => ( 6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s7; - - FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - VARIABLE table : matrix := (0 => (13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7), - 1 => ( 1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2), - 2 => ( 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8), - 3 => ( 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11)); - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s8; - - FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31; - VARIABLE table : matrix := (15, 6, 19, 20, - 28, 11, 27, 16, - 0, 14, 22, 25, - 4, 17, 30, 9, - 1, 7, 23, 13, - 31, 26, 2, 8, - 18, 12, 29, 5, - 21, 10, 3, 24); - VARIABLE result : std_logic_vector(0 TO 31); - BEGIN - FOR index IN 0 TO 31 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION p; - - FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS - VARIABLE intern : std_logic_vector(0 TO 47); - VARIABLE result : std_logic_vector(0 TO 31); - BEGIN - intern := e( input_r ) xor input_key; - result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) & - s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) ); - RETURN result; - END FUNCTION f; - - FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63; - VARIABLE table : matrix := (56, 48, 40, 32, 24, 16, 8, - 0, 57, 49, 41, 33, 25, 17, - 9, 1, 58, 50, 42, 34, 26, - 18, 10, 2, 59, 51, 43, 35); - VARIABLE result : std_logic_vector(0 TO 27); - BEGIN - FOR index IN 0 TO 27 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc1_c; - - FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63; - VARIABLE table : matrix := (62, 54, 46, 38, 30, 22, 14, - 6, 61, 53, 45, 37, 29, 21, - 13, 5, 60, 52, 44, 36, 28, - 20, 12, 4, 27, 19, 11, 3); - VARIABLE result : std_logic_vector(0 TO 27); - BEGIN - FOR index IN 0 TO 27 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc1_d; - - FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS - TYPE matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63; - VARIABLE table : matrix := (13, 16, 10, 23, 0, 4, - 2, 27, 14, 5, 20, 9, - 22, 18, 11, 3, 25, 7, - 15, 6, 26, 19, 12, 1, - 40, 51, 30, 36, 46, 54, - 29, 39, 50, 44, 32, 47, - 43, 48, 38, 55, 33, 52, - 45, 41, 49, 35, 28, 31); - VARIABLE result : std_logic_vector(0 TO 47); - BEGIN - FOR index IN 0 TO 47 LOOP - result( index ) := input_vector( table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc2; - - -END PACKAGE BODY des_pkg; \ No newline at end of file diff --git a/tdes/rtl/tdes.vhd b/tdes/rtl/tdes.vhd deleted file mode 100644 index 087aa4c..0000000 --- a/tdes/rtl/tdes.vhd +++ /dev/null @@ -1,168 +0,0 @@ --- ====================================================================== --- TDES encryption/decryption --- algorithm according to FIPS 46-3 specification --- Copyright (C) 2011 Torsten Meissner -------------------------------------------------------------------------- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. - --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. - --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA --- ====================================================================== - - --- Revision 0.1 2011/10/08 --- Initial release - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.des_pkg.all; - - -entity tdes is - port ( - reset_i : in std_logic; -- async reset - clk_i : in std_logic; -- clock - mode_i : in std_logic; -- tdes-modus: 0 = encrypt, 1 = decrypt - key1_i : in std_logic_vector(0 TO 63); -- key input - key2_i : in std_logic_vector(0 TO 63); -- key input - key3_i : in std_logic_vector(0 TO 63); -- key input - data_i : in std_logic_vector(0 TO 63); -- data input - valid_i : in std_logic; -- input key/data valid flag - data_o : out std_logic_vector(0 TO 63); -- data output - valid_o : out std_logic; -- output data valid flag - ready_o : out std_logic - ); -end entity tdes; - - -architecture rtl of tdes is - - - component des is - port ( - reset_i : in std_logic; - clk_i : IN std_logic; -- clock - mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt - key_i : IN std_logic_vector(0 TO 63); -- key input - data_i : IN std_logic_vector(0 TO 63); -- data input - valid_i : IN std_logic; -- input key/data valid flag - data_o : OUT std_logic_vector(0 TO 63); -- data output - valid_o : OUT std_logic -- output data valid flag - ); - end component des; - - - signal s_ready : std_logic; - signal s_reset : std_logic; - signal s_mode : std_logic; - signal s_des2_mode : std_logic; - signal s_des1_validin : std_logic := '0'; - signal s_des1_validout : std_logic; - signal s_des2_validout : std_logic; - signal s_des3_validout : std_logic; - signal s_key1 : std_logic_vector(0 to 63); - signal s_key2 : std_logic_vector(0 to 63); - signal s_key3 : std_logic_vector(0 to 63); - signal s_des1_key : std_logic_vector(0 to 63); - signal s_des3_key : std_logic_vector(0 to 63); - signal s_des1_dataout : std_logic_vector(0 to 63); - signal s_des2_dataout : std_logic_vector(0 to 63); - -begin - - - ready_o <= s_ready; - valid_o <= s_des3_validout; - s_des2_mode <= not(s_mode); - s_des1_validin <= valid_i and s_ready; - - s_des1_key <= key1_i when mode_i = '0' else key3_i; - s_des3_key <= s_key3 when s_mode = '0' else s_key1; - - - inputregister : process(clk_i, reset_i) is - begin - if(reset_i = '0') then - s_reset <= '0'; - s_mode <= '0'; - s_key1 <= (others => '0'); - s_key2 <= (others => '0'); - s_key3 <= (others => '0'); - elsif(rising_edge(clk_i)) then - s_reset <= reset_i; - if(valid_i = '1' and s_ready = '1') then - s_mode <= mode_i; - s_key1 <= key1_i; - s_key2 <= key2_i; - s_key3 <= key3_i; - end if; - end if; - end process inputregister; - - - outputregister : process(clk_i, reset_i) is - begin - if(reset_i = '0') then - s_ready <= '0'; - elsif(rising_edge(clk_i)) then - if(valid_i = '1' and s_ready = '1') then - s_ready <= '0'; - end if; - if(s_des3_validout = '1' or (reset_i = '1' and s_reset = '0')) then - s_ready <= '1'; - end if; - end if; - end process outputregister; - - - i1_des : des - port map ( - reset_i => reset_i, - clk_i => clk_i, - mode_i => mode_i, - key_i => s_des1_key, - data_i => data_i, - valid_i => s_des1_validin, - data_o => s_des1_dataout, - valid_o => s_des1_validout - ); - - - i2_des : des - port map ( - reset_i => reset_i, - clk_i => clk_i, - mode_i => s_des2_mode, - key_i => s_key2, - data_i => s_des1_dataout, - valid_i => s_des1_validout, - data_o => s_des2_dataout, - valid_o => s_des2_validout - ); - - - i3_des : des - port map ( - reset_i => reset_i, - clk_i => clk_i, - mode_i => s_mode, - key_i => s_des3_key, - data_i => s_des2_dataout, - valid_i => s_des2_validout, - data_o => data_o, - valid_o => s_des3_validout - ); - - -end architecture rtl; From d779f5aebedfaa3ac3d91ad06cae89eaeab6a081 Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Sun, 24 Mar 2013 15:59:10 +0100 Subject: [PATCH 2/8] moved into seperate vhdl folder --- tdes/rtl/vhdl/des.vhd | 340 ++++++++++++++++++++++++++++++++++++++ tdes/rtl/vhdl/des_pkg.vhd | 333 +++++++++++++++++++++++++++++++++++++ tdes/rtl/vhdl/tdes.vhd | 168 +++++++++++++++++++ 3 files changed, 841 insertions(+) create mode 100644 tdes/rtl/vhdl/des.vhd create mode 100644 tdes/rtl/vhdl/des_pkg.vhd create mode 100644 tdes/rtl/vhdl/tdes.vhd diff --git a/tdes/rtl/vhdl/des.vhd b/tdes/rtl/vhdl/des.vhd new file mode 100644 index 0000000..9ebc905 --- /dev/null +++ b/tdes/rtl/vhdl/des.vhd @@ -0,0 +1,340 @@ +-- ====================================================================== +-- DES encryption/decryption +-- algorithm according to FIPS 46-3 specification +-- Copyright (C) 2007 Torsten Meissner +------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- ====================================================================== + + +-- Revision 1.0 2007/02/04 +-- Initial release +-- Revision 1.1 2007/02/05 +-- Corrected error in use of mode register for key calculation + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.ALL; +USE work.des_pkg.ALL; + + +ENTITY des IS + PORT ( + reset_i : in std_logic; -- async reset + clk_i : IN std_logic; -- clock + mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt + key_i : IN std_logic_vector(0 TO 63); -- key input + data_i : IN std_logic_vector(0 TO 63); -- data input + valid_i : IN std_logic; -- input key/data valid flag + data_o : OUT std_logic_vector(0 TO 63); -- data output + valid_o : OUT std_logic -- output data valid flag + ); +END ENTITY des; + + +ARCHITECTURE rtl OF des IS + +BEGIN + + crypt : PROCESS ( clk_i ) IS + -- variables for key calculation + VARIABLE c0 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c1 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c2 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c3 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c4 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c5 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c6 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c7 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c8 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c9 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d0 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d1 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d2 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d3 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d4 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d5 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d6 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d7 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d8 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d9 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0'); + -- key variables + VARIABLE key1 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key2 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key3 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key4 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key5 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key6 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key7 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key8 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key9 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0'); + -- variables for left & right data blocks + VARIABLE l0 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l1 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l2 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l3 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l4 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l5 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l6 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l7 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l8 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l9 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r0 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r1 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r2 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r3 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r4 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r5 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r6 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r7 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r8 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r9 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0'); + -- variables for mode & valid shift registers + VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0'); + VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0'); + BEGIN + if(reset_i = '0') then + data_o <= (others => '0'); + valid_o <= '0'; + elsif rising_edge( clk_i ) THEN + -- shift registers + valid(1 TO 17) := valid(0 TO 16); + valid(0) := valid_i; + mode(1 TO 16) := mode(0 TO 15); + mode(0) := mode_i; + -- output stage + valid_o <= valid(17); + data_o <= ipn( ( r16 & l16 ) ); + -- 16. stage + IF mode(16) = '0' THEN + c16 := c15(1 TO 27) & c15(0); + d16 := d15(1 TO 27) & d15(0); + ELSE + c16 := c15(27) & c15(0 TO 26); + d16 := d15(27) & d15(0 TO 26); + END IF; + key16 := pc2( ( c16 & d16 ) ); + l16 := r15; + r16 := l15 xor ( f( r15, key16 ) ); + -- 15. stage + IF mode(15) = '0' THEN + c15 := c14(2 TO 27) & c14(0 TO 1); + d15 := d14(2 TO 27) & d14(0 TO 1); + ELSE + c15 := c14(26 TO 27) & c14(0 TO 25); + d15 := d14(26 TO 27) & d14(0 TO 25); + END IF; + key15 := pc2( ( c15 & d15 ) ); + l15 := r14; + r15 := l14 xor ( f( r14, key15 ) ); + -- 14. stage + IF mode(14) = '0' THEN + c14 := c13(2 TO 27) & c13(0 TO 1); + d14 := d13(2 TO 27) & d13(0 TO 1); + ELSE + c14 := c13(26 TO 27) & c13(0 TO 25); + d14 := d13(26 TO 27) & d13(0 TO 25); + END IF; + key14 := pc2( ( c14 & d14 ) ); + l14 := r13; + r14 := l13 xor ( f( r13, key14 ) ); + -- 13. stage + IF mode(13) = '0' THEN + c13 := c12(2 TO 27) & c12(0 TO 1); + d13 := d12(2 TO 27) & d12(0 TO 1); + ELSE + c13 := c12(26 TO 27) & c12(0 TO 25); + d13 := d12(26 TO 27) & d12(0 TO 25); + END IF; + key13 := pc2( ( c13 & d13 ) ); + l13 := r12; + r13 := l12 xor ( f( r12, key13 ) ); + -- 12. stage + IF mode(12) = '0' THEN + c12 := c11(2 TO 27) & c11(0 TO 1); + d12 := d11(2 TO 27) & d11(0 TO 1); + ELSE + c12 := c11(26 TO 27) & c11(0 TO 25); + d12 := d11(26 TO 27) & d11(0 TO 25); + END IF; + key12 := pc2( ( c12 & d12 ) ); + l12 := r11; + r12 := l11 xor ( f( r11, key12 ) ); + -- 11. stage + IF mode(11) = '0' THEN + c11 := c10(2 TO 27) & c10(0 TO 1); + d11 := d10(2 TO 27) & d10(0 TO 1); + ELSE + c11 := c10(26 TO 27) & c10(0 TO 25); + d11 := d10(26 TO 27) & d10(0 TO 25); + END IF; + key11 := pc2( ( c11 & d11 ) ); + l11 := r10; + r11 := l10 xor ( f( r10, key11 ) ); + -- 10. stage + IF mode(10) = '0' THEN + c10 := c9(2 TO 27) & c9(0 TO 1); + d10 := d9(2 TO 27) & d9(0 TO 1); + ELSE + c10 := c9(26 TO 27) & c9(0 TO 25); + d10 := d9(26 TO 27) & d9(0 TO 25); + END IF; + key10 := pc2( ( c10 & d10 ) ); + l10 := r9; + r10 := l9 xor ( f( r9, key10 ) ); + -- 9. stage + IF mode(9) = '0' THEN + c9 := c8(1 TO 27) & c8(0); + d9 := d8(1 TO 27) & d8(0); + ELSE + c9 := c8(27) & c8(0 TO 26); + d9 := d8(27) & d8(0 TO 26); + END IF; + key9 := pc2( ( c9 & d9 ) ); + l9 := r8; + r9 := l8 xor ( f( r8, key9 ) ); + -- 8. stage + IF mode(8) = '0' THEN + c8 := c7(2 TO 27) & c7(0 TO 1); + d8 := d7(2 TO 27) & d7(0 TO 1); + ELSE + c8 := c7(26 TO 27) & c7(0 TO 25); + d8 := d7(26 TO 27) & d7(0 TO 25); + END IF; + key8 := pc2( ( c8 & d8 ) ); + l8 := r7; + r8 := l7 xor ( f( r7, key8 ) ); + -- 7. stage + IF mode(7) = '0' THEN + c7 := c6(2 TO 27) & c6(0 TO 1); + d7 := d6(2 TO 27) & d6(0 TO 1); + ELSE + c7 := c6(26 TO 27) & c6(0 TO 25); + d7 := d6(26 TO 27) & d6(0 TO 25); + END IF; + key7 := pc2( ( c7 & d7 ) ); + l7 := r6; + r7 := l6 xor ( f( r6, key7 ) ); + -- 6. stage + IF mode(6) = '0' THEN + c6 := c5(2 TO 27) & c5(0 TO 1); + d6 := d5(2 TO 27) & d5(0 TO 1); + ELSE + c6 := c5(26 TO 27) & c5(0 TO 25); + d6 := d5(26 TO 27) & d5(0 TO 25); + END IF; + key6 := pc2( ( c6 & d6 ) ); + l6 := r5; + r6 := l5 xor ( f( r5, key6 ) ); + -- 5. stage + IF mode(5) = '0' THEN + c5 := c4(2 TO 27) & c4(0 TO 1); + d5 := d4(2 TO 27) & d4(0 TO 1); + ELSE + c5 := c4(26 TO 27) & c4(0 TO 25); + d5 := d4(26 TO 27) & d4(0 TO 25); + END IF; + key5 := pc2( ( c5 & d5 ) ); + l5 := r4; + r5 := l4 xor ( f( r4, key5 ) ); + -- 4. stage + IF mode(4) = '0' THEN + c4 := c3(2 TO 27) & c3(0 TO 1); + d4 := d3(2 TO 27) & d3(0 TO 1); + ELSE + c4 := c3(26 TO 27) & c3(0 TO 25); + d4 := d3(26 TO 27) & d3(0 TO 25); + END IF; + key4 := pc2( ( c4 & d4 ) ); + l4 := r3; + r4 := l3 xor ( f( r3, key4 ) ); + -- 3. stage + IF mode(3) = '0' THEN + c3 := c2(2 TO 27) & c2(0 TO 1); + d3 := d2(2 TO 27) & d2(0 TO 1); + ELSE + c3 := c2(26 TO 27) & c2(0 TO 25); + d3 := d2(26 TO 27) & d2(0 TO 25); + END IF; + key3 := pc2( ( c3 & d3 ) ); + l3 := r2; + r3 := l2 xor ( f( r2, key3 ) ); + -- 2. stage + IF mode(2) = '0' THEN + c2 := c1(1 TO 27) & c1(0); + d2 := d1(1 TO 27) & d1(0); + ELSE + c2 := c1(27) & c1(0 TO 26); + d2 := d1(27) & d1(0 TO 26); + END IF; + key2 := pc2( ( c2 & d2 ) ); + l2 := r1; + r2 := l1 xor ( f( r1, key2 ) ); + -- 1. stage + IF mode(1) = '0' THEN + c1 := c0(1 TO 27) & c0(0); + d1 := d0(1 TO 27) & d0(0); + ELSE + c1 := c0; + d1 := d0; + END IF; + key1 := pc2( ( c1 & d1 ) ); + l1 := r0; + r1 := l0 xor ( f( r0, key1 ) ); + -- input stage + l0 := ip( data_i )(0 TO 31); + r0 := ip( data_i )(32 TO 63); + c0 := pc1_c( key_i ); + d0 := pc1_d( key_i ); + END IF; + END PROCESS crypt; + +END ARCHITECTURE rtl; diff --git a/tdes/rtl/vhdl/des_pkg.vhd b/tdes/rtl/vhdl/des_pkg.vhd new file mode 100644 index 0000000..384209e --- /dev/null +++ b/tdes/rtl/vhdl/des_pkg.vhd @@ -0,0 +1,333 @@ +-- ====================================================================== +-- DES encryption/decryption +-- package file with functions +-- Copyright (C) 2007 Torsten Meissner +------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- ====================================================================== + + +-- Revision 1.0 2007/02/04 +-- Initial release + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.ALL; + + +PACKAGE des_pkg IS + + FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; + FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; + + FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; + FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; + + FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + + FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector; + + FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; + FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; + FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector; + +END PACKAGE des_pkg; + + +PACKAGE BODY des_pkg IS + + FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63; + VARIABLE table : matrix := (57, 49, 41, 33, 25, 17, 9, 1, + 59, 51, 43, 35, 27, 19, 11, 3, + 61, 53, 45, 37, 29, 21, 13, 5, + 63, 55, 47, 39, 31, 23, 15, 7, + 56, 48, 40, 32, 24, 16, 8, 0, + 58, 50, 42, 34, 26, 18, 10, 2, + 60, 52, 44, 36, 28, 20, 12, 4, + 62, 54, 46, 38, 30, 22, 14, 6); + VARIABLE result : std_logic_vector(0 TO 63); + BEGIN + FOR index IN 0 TO 63 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION ip; + + FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63; + VARIABLE table : matrix := (39, 7, 47, 15, 55, 23, 63, 31, + 38, 6, 46, 14, 54, 22, 62, 30, + 37, 5, 45, 13, 53, 21, 61, 29, + 36, 4, 44, 12, 52, 20, 60, 28, + 35, 3, 43, 11, 51, 19, 59, 27, + 34, 2, 42, 10, 50, 18, 58, 26, + 33, 1, 41, 9, 49, 17, 57, 25, + 32, 0, 40, 8, 48, 16, 56, 24); + VARIABLE result : std_logic_vector(0 TO 63); + BEGIN + FOR index IN 0 TO 63 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION ipn; + + FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31; + VARIABLE table : matrix := (31, 0, 1, 2, 3, 4, + 3, 4, 5, 6, 7, 8, + 7, 8, 9, 10, 11, 12, + 11, 12, 13, 14, 15, 16, + 15, 16, 17, 18, 19, 20, + 19, 20, 21, 22, 23, 24, + 23, 24, 25, 26, 27, 28, + 27, 28, 29, 30, 31, 0); + VARIABLE result : std_logic_vector(0 TO 47); + BEGIN + FOR index IN 0 TO 47 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION e; + + FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => (14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7), + 1 => ( 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8), + 2 => ( 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0), + 3 => (15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s1; + + FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => (15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10), + 1 => ( 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5), + 2 => ( 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15), + 3 => (13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s2; + + FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => (10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8), + 1 => (13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1), + 2 => (13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7), + 3 => ( 1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s3; + + FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => ( 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15), + 1 => (13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9), + 2 => (10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4), + 3 => ( 3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s4; + + FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => ( 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9), + 1 => (14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6), + 2 => ( 4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14), + 3 => (11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s5; + + FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => (12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11), + 1 => (10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8), + 2 => ( 9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6), + 3 => ( 4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s6; + + FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => ( 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1), + 1 => (13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6), + 2 => ( 1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2), + 3 => ( 6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s7; + + FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => (13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7), + 1 => ( 1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2), + 2 => ( 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8), + 3 => ( 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s8; + + FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31; + VARIABLE table : matrix := (15, 6, 19, 20, + 28, 11, 27, 16, + 0, 14, 22, 25, + 4, 17, 30, 9, + 1, 7, 23, 13, + 31, 26, 2, 8, + 18, 12, 29, 5, + 21, 10, 3, 24); + VARIABLE result : std_logic_vector(0 TO 31); + BEGIN + FOR index IN 0 TO 31 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION p; + + FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS + VARIABLE intern : std_logic_vector(0 TO 47); + VARIABLE result : std_logic_vector(0 TO 31); + BEGIN + intern := e( input_r ) xor input_key; + result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) & + s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) ); + RETURN result; + END FUNCTION f; + + FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63; + VARIABLE table : matrix := (56, 48, 40, 32, 24, 16, 8, + 0, 57, 49, 41, 33, 25, 17, + 9, 1, 58, 50, 42, 34, 26, + 18, 10, 2, 59, 51, 43, 35); + VARIABLE result : std_logic_vector(0 TO 27); + BEGIN + FOR index IN 0 TO 27 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION pc1_c; + + FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63; + VARIABLE table : matrix := (62, 54, 46, 38, 30, 22, 14, + 6, 61, 53, 45, 37, 29, 21, + 13, 5, 60, 52, 44, 36, 28, + 20, 12, 4, 27, 19, 11, 3); + VARIABLE result : std_logic_vector(0 TO 27); + BEGIN + FOR index IN 0 TO 27 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION pc1_d; + + FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63; + VARIABLE table : matrix := (13, 16, 10, 23, 0, 4, + 2, 27, 14, 5, 20, 9, + 22, 18, 11, 3, 25, 7, + 15, 6, 26, 19, 12, 1, + 40, 51, 30, 36, 46, 54, + 29, 39, 50, 44, 32, 47, + 43, 48, 38, 55, 33, 52, + 45, 41, 49, 35, 28, 31); + VARIABLE result : std_logic_vector(0 TO 47); + BEGIN + FOR index IN 0 TO 47 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION pc2; + + +END PACKAGE BODY des_pkg; \ No newline at end of file diff --git a/tdes/rtl/vhdl/tdes.vhd b/tdes/rtl/vhdl/tdes.vhd new file mode 100644 index 0000000..087aa4c --- /dev/null +++ b/tdes/rtl/vhdl/tdes.vhd @@ -0,0 +1,168 @@ +-- ====================================================================== +-- TDES encryption/decryption +-- algorithm according to FIPS 46-3 specification +-- Copyright (C) 2011 Torsten Meissner +------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- ====================================================================== + + +-- Revision 0.1 2011/10/08 +-- Initial release + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.des_pkg.all; + + +entity tdes is + port ( + reset_i : in std_logic; -- async reset + clk_i : in std_logic; -- clock + mode_i : in std_logic; -- tdes-modus: 0 = encrypt, 1 = decrypt + key1_i : in std_logic_vector(0 TO 63); -- key input + key2_i : in std_logic_vector(0 TO 63); -- key input + key3_i : in std_logic_vector(0 TO 63); -- key input + data_i : in std_logic_vector(0 TO 63); -- data input + valid_i : in std_logic; -- input key/data valid flag + data_o : out std_logic_vector(0 TO 63); -- data output + valid_o : out std_logic; -- output data valid flag + ready_o : out std_logic + ); +end entity tdes; + + +architecture rtl of tdes is + + + component des is + port ( + reset_i : in std_logic; + clk_i : IN std_logic; -- clock + mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt + key_i : IN std_logic_vector(0 TO 63); -- key input + data_i : IN std_logic_vector(0 TO 63); -- data input + valid_i : IN std_logic; -- input key/data valid flag + data_o : OUT std_logic_vector(0 TO 63); -- data output + valid_o : OUT std_logic -- output data valid flag + ); + end component des; + + + signal s_ready : std_logic; + signal s_reset : std_logic; + signal s_mode : std_logic; + signal s_des2_mode : std_logic; + signal s_des1_validin : std_logic := '0'; + signal s_des1_validout : std_logic; + signal s_des2_validout : std_logic; + signal s_des3_validout : std_logic; + signal s_key1 : std_logic_vector(0 to 63); + signal s_key2 : std_logic_vector(0 to 63); + signal s_key3 : std_logic_vector(0 to 63); + signal s_des1_key : std_logic_vector(0 to 63); + signal s_des3_key : std_logic_vector(0 to 63); + signal s_des1_dataout : std_logic_vector(0 to 63); + signal s_des2_dataout : std_logic_vector(0 to 63); + +begin + + + ready_o <= s_ready; + valid_o <= s_des3_validout; + s_des2_mode <= not(s_mode); + s_des1_validin <= valid_i and s_ready; + + s_des1_key <= key1_i when mode_i = '0' else key3_i; + s_des3_key <= s_key3 when s_mode = '0' else s_key1; + + + inputregister : process(clk_i, reset_i) is + begin + if(reset_i = '0') then + s_reset <= '0'; + s_mode <= '0'; + s_key1 <= (others => '0'); + s_key2 <= (others => '0'); + s_key3 <= (others => '0'); + elsif(rising_edge(clk_i)) then + s_reset <= reset_i; + if(valid_i = '1' and s_ready = '1') then + s_mode <= mode_i; + s_key1 <= key1_i; + s_key2 <= key2_i; + s_key3 <= key3_i; + end if; + end if; + end process inputregister; + + + outputregister : process(clk_i, reset_i) is + begin + if(reset_i = '0') then + s_ready <= '0'; + elsif(rising_edge(clk_i)) then + if(valid_i = '1' and s_ready = '1') then + s_ready <= '0'; + end if; + if(s_des3_validout = '1' or (reset_i = '1' and s_reset = '0')) then + s_ready <= '1'; + end if; + end if; + end process outputregister; + + + i1_des : des + port map ( + reset_i => reset_i, + clk_i => clk_i, + mode_i => mode_i, + key_i => s_des1_key, + data_i => data_i, + valid_i => s_des1_validin, + data_o => s_des1_dataout, + valid_o => s_des1_validout + ); + + + i2_des : des + port map ( + reset_i => reset_i, + clk_i => clk_i, + mode_i => s_des2_mode, + key_i => s_key2, + data_i => s_des1_dataout, + valid_i => s_des1_validout, + data_o => s_des2_dataout, + valid_o => s_des2_validout + ); + + + i3_des : des + port map ( + reset_i => reset_i, + clk_i => clk_i, + mode_i => s_mode, + key_i => s_des3_key, + data_i => s_des2_dataout, + valid_i => s_des2_validout, + data_o => data_o, + valid_o => s_des3_validout + ); + + +end architecture rtl; From 5e422923cf31472a34afce91e9f599f17ab44687 Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Sun, 24 Mar 2013 16:00:21 +0100 Subject: [PATCH 3/8] moved into seperate vhdl folder --- tdes/sim/makefile | 37 --------- tdes/sim/tb_tdes.tcl | 13 ---- tdes/sim/tb_tdes.vhd | 177 ------------------------------------------- 3 files changed, 227 deletions(-) delete mode 100644 tdes/sim/makefile delete mode 100644 tdes/sim/tb_tdes.tcl delete mode 100644 tdes/sim/tb_tdes.vhd diff --git a/tdes/sim/makefile b/tdes/sim/makefile deleted file mode 100644 index 1d54344..0000000 --- a/tdes/sim/makefile +++ /dev/null @@ -1,37 +0,0 @@ -# ====================================================================== -# DES encryption/decryption -# algorithm according to FIPS 46-3 specification -# Copyright (C) 2011 Torsten Meissner -#----------------------------------------------------------------------- -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# ====================================================================== - - -all : sim wave - -sim : tb_tdes.ghw - -tb_tdes.ghw : ../rtl/*.vhd tb_tdes.vhd - ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/tdes.vhd tb_tdes.vhd - ghdl -e tb_tdes - ghdl -r tb_tdes --wave=tb_tdes.ghw --assert-level=error --stop-time=45us - -wave : tb_tdes.ghw - gtkwave -T tb_tdes.tcl tb_tdes.ghw - -clean : - echo "# cleaning simulation files" - rm -f *.ghw - rm -f work*.cf diff --git a/tdes/sim/tb_tdes.tcl b/tdes/sim/tb_tdes.tcl deleted file mode 100644 index 0dd3826..0000000 --- a/tdes/sim/tb_tdes.tcl +++ /dev/null @@ -1,13 +0,0 @@ -set signals [list] -lappend signals "top.tb_tdes.s_reset" -lappend signals "top.tb_tdes.s_clk" -lappend signals "top.tb_tdes.s_validin" -lappend signals "top.tb_tdes.s_mode" -lappend signals "top.tb_tdes.s_key1" -lappend signals "top.tb_tdes.s_key2" -lappend signals "top.tb_tdes.s_key3" -lappend signals "top.tb_tdes.s_datain" -lappend signals "top.tb_tdes.s_validout" -lappend signals "top.tb_tdes.s_dataout" -lappend signals "top.tb_tdes.s_ready" -set num_added [ gtkwave::addSignalsFromList $signals ] diff --git a/tdes/sim/tb_tdes.vhd b/tdes/sim/tb_tdes.vhd deleted file mode 100644 index d60bb69..0000000 --- a/tdes/sim/tb_tdes.vhd +++ /dev/null @@ -1,177 +0,0 @@ --- ====================================================================== --- TDES encryption/decryption testbench --- tests according to NIST 800-17 special publication --- Copyright (C) 2011 Torsten Meissner -------------------------------------------------------------------------- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. - --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. - --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA --- ====================================================================== - - --- Revision 0.1 2011/10/08 --- Initial release - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity tb_tdes is -end entity tb_tdes; - - -architecture rtl of tb_tdes is - - - type t_array is array (natural range <>) of std_logic_vector(0 to 63); - - constant c_table_test_plain : t_array(0 to 18) := - (x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172", - x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A", - x"0756D8E0774761D2", x"762514B829BF486A", x"3BDD119049372802", - x"26955F6835AF609A", x"164D5E404F275232", x"6B056E18759F5CCA", - x"004BD6EF09176062", x"480D39006EE762F2", x"437540C8698F3CFA", - x"072D43A077075292", x"02FE55778117F12A", x"1D9D5C5018F728C2", - x"305532286D6F295A"); - - signal s_tdes_answers : t_array(0 to 19); - - signal s_reset : std_logic := '0'; - signal s_clk : std_logic := '0'; - signal s_mode : std_logic := '0'; - signal s_key1 : std_logic_vector(0 to 63) := (others => '0'); - signal s_key2 : std_logic_vector(0 to 63) := (others => '0'); - signal s_key3 : std_logic_vector(0 to 63) := (others => '0'); - signal s_datain : std_logic_vector(0 to 63) := (others => '0'); - signal s_validin : std_logic := '0'; - signal s_ready : std_logic := '0'; - signal s_dataout : std_logic_vector(0 to 63); - signal s_validout : std_logic := '0'; - - - component tdes is - port ( - reset_i : in std_logic; - clk_i : in std_logic; - mode_i : in std_logic; - key1_i : in std_logic_vector(0 to 63); - key2_i : in std_logic_vector(0 TO 63); - key3_i : in std_logic_vector(0 TO 63); - data_i : in std_logic_vector(0 TO 63); - valid_i : in std_logic; - data_o : out std_logic_vector(0 TO 63); - valid_o : out std_logic; - ready_o : out std_logic - ); - end component tdes; - - -begin - - - s_reset <= '1' after 100 ns; - s_clk <= not(s_clk) after 10 ns; - - - teststimuliP : process is - begin - s_mode <= '0'; - s_validin <= '0'; - s_key1 <= (others => '0'); - s_key2 <= (others => '0'); - s_key3 <= (others => '0'); - s_datain <= (others => '0'); - -- ENCRYPTION TESTS - -- cbc known answers test - for index in c_table_test_plain'range loop - wait until rising_edge(s_clk) and s_ready = '1'; - s_key1 <= x"1111111111111111"; - s_key2 <= x"5555555555555555"; - s_key3 <= x"9999999999999999"; - s_validin <= '1'; - s_datain <= c_table_test_plain(index); - wait until rising_edge(s_clk); - s_validin <= '0'; - end loop; - wait until rising_edge(s_clk); - s_mode <= '0'; - s_validin <= '0'; - s_key1 <= (others => '0'); - s_key2 <= (others => '0'); - s_key3 <= (others => '0'); - s_datain <= (others => '0'); - wait for 1 us; - -- DECRYPTION TESTS - -- cbc known answer test - for index in c_table_test_plain'range loop - wait until rising_edge(s_clk) and s_ready = '1'; - s_key1 <= x"1111111111111111"; - s_key2 <= x"5555555555555555"; - s_key3 <= x"9999999999999999"; - s_mode <= '1'; - s_validin <= '1'; - s_datain <= s_tdes_answers(index); - wait until rising_edge(s_clk); - s_validin <= '0'; - s_mode <= '0'; - end loop; - wait until rising_edge(s_clk); - s_mode <= '0'; - s_validin <= '0'; - s_key1 <= (others => '0'); - s_key2 <= (others => '0'); - s_key3 <= (others => '0'); - s_datain <= (others => '0'); - wait; - end process teststimuliP; - - - testcheckerP : process is - begin - report "# ENCRYPTION TESTS"; - for index in c_table_test_plain'range loop - wait until rising_edge(s_clk) and s_validout = '1'; - s_tdes_answers(index) <= s_dataout; - end loop; - report "# DECRYPTION TESTS"; - report "# tdes known answer test"; - for index in c_table_test_plain'range loop - wait until rising_edge(s_clk) and s_validout = '1'; - assert (s_dataout = c_table_test_plain(index)) - report "decryption error" - severity error; - end loop; - report "# Successfully passed all tests"; - wait; - end process testcheckerP; - - - i_tdes : tdes - port map ( - reset_i => s_reset, - clk_i => s_clk, - mode_i => s_mode, - key1_i => s_key1, - key2_i => s_key2, - key3_i => s_key3, - data_i => s_datain, - valid_i => s_validin, - data_o => s_dataout, - valid_o => s_validout, - ready_o => s_ready - ); - - -end architecture rtl; From 30a7af4830e3ca99ff14e632976c5cf2c82321a8 Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Sun, 24 Mar 2013 16:00:37 +0100 Subject: [PATCH 4/8] moved into seperate vhdl folder --- tdes/sim/vhdl/makefile | 37 ++++++++ tdes/sim/vhdl/tb_tdes.tcl | 13 +++ tdes/sim/vhdl/tb_tdes.vhd | 177 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 227 insertions(+) create mode 100644 tdes/sim/vhdl/makefile create mode 100644 tdes/sim/vhdl/tb_tdes.tcl create mode 100644 tdes/sim/vhdl/tb_tdes.vhd diff --git a/tdes/sim/vhdl/makefile b/tdes/sim/vhdl/makefile new file mode 100644 index 0000000..1d54344 --- /dev/null +++ b/tdes/sim/vhdl/makefile @@ -0,0 +1,37 @@ +# ====================================================================== +# DES encryption/decryption +# algorithm according to FIPS 46-3 specification +# Copyright (C) 2011 Torsten Meissner +#----------------------------------------------------------------------- +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# ====================================================================== + + +all : sim wave + +sim : tb_tdes.ghw + +tb_tdes.ghw : ../rtl/*.vhd tb_tdes.vhd + ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/tdes.vhd tb_tdes.vhd + ghdl -e tb_tdes + ghdl -r tb_tdes --wave=tb_tdes.ghw --assert-level=error --stop-time=45us + +wave : tb_tdes.ghw + gtkwave -T tb_tdes.tcl tb_tdes.ghw + +clean : + echo "# cleaning simulation files" + rm -f *.ghw + rm -f work*.cf diff --git a/tdes/sim/vhdl/tb_tdes.tcl b/tdes/sim/vhdl/tb_tdes.tcl new file mode 100644 index 0000000..0dd3826 --- /dev/null +++ b/tdes/sim/vhdl/tb_tdes.tcl @@ -0,0 +1,13 @@ +set signals [list] +lappend signals "top.tb_tdes.s_reset" +lappend signals "top.tb_tdes.s_clk" +lappend signals "top.tb_tdes.s_validin" +lappend signals "top.tb_tdes.s_mode" +lappend signals "top.tb_tdes.s_key1" +lappend signals "top.tb_tdes.s_key2" +lappend signals "top.tb_tdes.s_key3" +lappend signals "top.tb_tdes.s_datain" +lappend signals "top.tb_tdes.s_validout" +lappend signals "top.tb_tdes.s_dataout" +lappend signals "top.tb_tdes.s_ready" +set num_added [ gtkwave::addSignalsFromList $signals ] diff --git a/tdes/sim/vhdl/tb_tdes.vhd b/tdes/sim/vhdl/tb_tdes.vhd new file mode 100644 index 0000000..d60bb69 --- /dev/null +++ b/tdes/sim/vhdl/tb_tdes.vhd @@ -0,0 +1,177 @@ +-- ====================================================================== +-- TDES encryption/decryption testbench +-- tests according to NIST 800-17 special publication +-- Copyright (C) 2011 Torsten Meissner +------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- ====================================================================== + + +-- Revision 0.1 2011/10/08 +-- Initial release + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity tb_tdes is +end entity tb_tdes; + + +architecture rtl of tb_tdes is + + + type t_array is array (natural range <>) of std_logic_vector(0 to 63); + + constant c_table_test_plain : t_array(0 to 18) := + (x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172", + x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A", + x"0756D8E0774761D2", x"762514B829BF486A", x"3BDD119049372802", + x"26955F6835AF609A", x"164D5E404F275232", x"6B056E18759F5CCA", + x"004BD6EF09176062", x"480D39006EE762F2", x"437540C8698F3CFA", + x"072D43A077075292", x"02FE55778117F12A", x"1D9D5C5018F728C2", + x"305532286D6F295A"); + + signal s_tdes_answers : t_array(0 to 19); + + signal s_reset : std_logic := '0'; + signal s_clk : std_logic := '0'; + signal s_mode : std_logic := '0'; + signal s_key1 : std_logic_vector(0 to 63) := (others => '0'); + signal s_key2 : std_logic_vector(0 to 63) := (others => '0'); + signal s_key3 : std_logic_vector(0 to 63) := (others => '0'); + signal s_datain : std_logic_vector(0 to 63) := (others => '0'); + signal s_validin : std_logic := '0'; + signal s_ready : std_logic := '0'; + signal s_dataout : std_logic_vector(0 to 63); + signal s_validout : std_logic := '0'; + + + component tdes is + port ( + reset_i : in std_logic; + clk_i : in std_logic; + mode_i : in std_logic; + key1_i : in std_logic_vector(0 to 63); + key2_i : in std_logic_vector(0 TO 63); + key3_i : in std_logic_vector(0 TO 63); + data_i : in std_logic_vector(0 TO 63); + valid_i : in std_logic; + data_o : out std_logic_vector(0 TO 63); + valid_o : out std_logic; + ready_o : out std_logic + ); + end component tdes; + + +begin + + + s_reset <= '1' after 100 ns; + s_clk <= not(s_clk) after 10 ns; + + + teststimuliP : process is + begin + s_mode <= '0'; + s_validin <= '0'; + s_key1 <= (others => '0'); + s_key2 <= (others => '0'); + s_key3 <= (others => '0'); + s_datain <= (others => '0'); + -- ENCRYPTION TESTS + -- cbc known answers test + for index in c_table_test_plain'range loop + wait until rising_edge(s_clk) and s_ready = '1'; + s_key1 <= x"1111111111111111"; + s_key2 <= x"5555555555555555"; + s_key3 <= x"9999999999999999"; + s_validin <= '1'; + s_datain <= c_table_test_plain(index); + wait until rising_edge(s_clk); + s_validin <= '0'; + end loop; + wait until rising_edge(s_clk); + s_mode <= '0'; + s_validin <= '0'; + s_key1 <= (others => '0'); + s_key2 <= (others => '0'); + s_key3 <= (others => '0'); + s_datain <= (others => '0'); + wait for 1 us; + -- DECRYPTION TESTS + -- cbc known answer test + for index in c_table_test_plain'range loop + wait until rising_edge(s_clk) and s_ready = '1'; + s_key1 <= x"1111111111111111"; + s_key2 <= x"5555555555555555"; + s_key3 <= x"9999999999999999"; + s_mode <= '1'; + s_validin <= '1'; + s_datain <= s_tdes_answers(index); + wait until rising_edge(s_clk); + s_validin <= '0'; + s_mode <= '0'; + end loop; + wait until rising_edge(s_clk); + s_mode <= '0'; + s_validin <= '0'; + s_key1 <= (others => '0'); + s_key2 <= (others => '0'); + s_key3 <= (others => '0'); + s_datain <= (others => '0'); + wait; + end process teststimuliP; + + + testcheckerP : process is + begin + report "# ENCRYPTION TESTS"; + for index in c_table_test_plain'range loop + wait until rising_edge(s_clk) and s_validout = '1'; + s_tdes_answers(index) <= s_dataout; + end loop; + report "# DECRYPTION TESTS"; + report "# tdes known answer test"; + for index in c_table_test_plain'range loop + wait until rising_edge(s_clk) and s_validout = '1'; + assert (s_dataout = c_table_test_plain(index)) + report "decryption error" + severity error; + end loop; + report "# Successfully passed all tests"; + wait; + end process testcheckerP; + + + i_tdes : tdes + port map ( + reset_i => s_reset, + clk_i => s_clk, + mode_i => s_mode, + key1_i => s_key1, + key2_i => s_key2, + key3_i => s_key3, + data_i => s_datain, + valid_i => s_validin, + data_o => s_dataout, + valid_o => s_validout, + ready_o => s_ready + ); + + +end architecture rtl; From 715b8b12291de466f2fabfaafac4b38d9aa21b0f Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Sun, 24 Mar 2013 16:05:13 +0100 Subject: [PATCH 5/8] beauty care --- tdes/sim/vhdl/tb_tdes.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tdes/sim/vhdl/tb_tdes.vhd b/tdes/sim/vhdl/tb_tdes.vhd index d60bb69..db05b46 100644 --- a/tdes/sim/vhdl/tb_tdes.vhd +++ b/tdes/sim/vhdl/tb_tdes.vhd @@ -170,7 +170,7 @@ begin valid_i => s_validin, data_o => s_dataout, valid_o => s_validout, - ready_o => s_ready + ready_o => s_ready ); From dd979b5cd38aa9e65be530e363a1dfea8753446e Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Sun, 24 Mar 2013 16:05:44 +0100 Subject: [PATCH 6/8] adapt makefile to new directory structure; new variable SRC_FILES for vhdl sources --- tdes/sim/vhdl/makefile | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tdes/sim/vhdl/makefile b/tdes/sim/vhdl/makefile index 1d54344..05b7eb8 100644 --- a/tdes/sim/vhdl/makefile +++ b/tdes/sim/vhdl/makefile @@ -19,12 +19,15 @@ # ====================================================================== +SRC_FILES = ../../rtl/vhdl/des_pkg.vhd ../../rtl/vhdl/des.vhd ../../rtl/vhdl/tdes.vhd + + all : sim wave sim : tb_tdes.ghw -tb_tdes.ghw : ../rtl/*.vhd tb_tdes.vhd - ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/tdes.vhd tb_tdes.vhd +tb_tdes.ghw : $(SRC_FILES) tb_tdes.vhd + ghdl -a $(SRC_FILES) tb_tdes.vhd ghdl -e tb_tdes ghdl -r tb_tdes --wave=tb_tdes.ghw --assert-level=error --stop-time=45us From 45403f17d1c50971c3bf37da31cef519ac9dfd0e Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Sun, 24 Mar 2013 16:07:15 +0100 Subject: [PATCH 7/8] import of des verilog design files --- tdes/rtl/verilog/des.v | 465 +++++++++++++++++++++++++++++++++++++ tdes/rtl/verilog/des_pkg.v | 246 ++++++++++++++++++++ 2 files changed, 711 insertions(+) create mode 100644 tdes/rtl/verilog/des.v create mode 100644 tdes/rtl/verilog/des_pkg.v diff --git a/tdes/rtl/verilog/des.v b/tdes/rtl/verilog/des.v new file mode 100644 index 0000000..633ac22 --- /dev/null +++ b/tdes/rtl/verilog/des.v @@ -0,0 +1,465 @@ +// ====================================================================== +// DES encryption/decryption +// algorithm according:FIPS 46-3 specification +// Copyright (C) 2012 Torsten Meissner +//----------------------------------------------------------------------- +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write:the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +// ====================================================================== + + +`timescale 1ns/1ps + + +module des + ( + input reset_i, // async reset + input clk_i, // clock + input mode_i, // des-mode: 0 = encrypt, 1 = decrypt + input [0:63] key_i, // key input + input [0:63] data_i, // data input + input valid_i, // input key/data valid flag + output reg [0:63] data_o, // data output + output valid_o // output data valid flag + ); + + +`include "../../rtl/verilog/des_pkg.v" + + // valid, mode register + reg [0:18] valid; + reg [0:17] mode; + + // algorithm pipeline register + // key calculation register + reg [0:27] c0; + reg [0:27] c1; + reg [0:27] c2; + reg [0:27] c3; + reg [0:27] c4; + reg [0:27] c5; + reg [0:27] c6; + reg [0:27] c7; + reg [0:27] c8; + reg [0:27] c9; + reg [0:27] c10; + reg [0:27] c11; + reg [0:27] c12; + reg [0:27] c13; + reg [0:27] c14; + reg [0:27] c15; + reg [0:27] c16; + reg [0:27] d0; + reg [0:27] d1; + reg [0:27] d2; + reg [0:27] d3; + reg [0:27] d4; + reg [0:27] d5; + reg [0:27] d6; + reg [0:27] d7; + reg [0:27] d8; + reg [0:27] d9; + reg [0:27] d10; + reg [0:27] d11; + reg [0:27] d12; + reg [0:27] d13; + reg [0:27] d14; + reg [0:27] d15; + reg [0:27] d16; + // key register + wire [0:47] key1; + wire [0:47] key2; + wire [0:47] key3; + wire [0:47] key4; + wire [0:47] key5; + wire [0:47] key6; + wire [0:47] key7; + wire [0:47] key8; + wire [0:47] key9; + wire [0:47] key10; + wire [0:47] key11; + wire [0:47] key12; + wire [0:47] key13; + wire [0:47] key14; + wire [0:47] key15; + wire [0:47] key16; + // register for left, right data blocks + reg [0:31] l; + reg [0:31] l0; + reg [0:31] l1; + reg [0:31] l2; + reg [0:31] l3; + reg [0:31] l4; + reg [0:31] l5; + reg [0:31] l6; + reg [0:31] l7; + reg [0:31] l8; + reg [0:31] l9; + reg [0:31] l10; + reg [0:31] l11; + reg [0:31] l12; + reg [0:31] l13; + reg [0:31] l14; + reg [0:31] l15; + reg [0:31] l16; + reg [0:31] r; + reg [0:31] r0; + reg [0:31] r1; + reg [0:31] r2; + reg [0:31] r3; + reg [0:31] r4; + reg [0:31] r5; + reg [0:31] r6; + reg [0:31] r7; + reg [0:31] r8; + reg [0:31] r9; + reg [0:31] r10; + reg [0:31] r11; + reg [0:31] r12; + reg [0:31] r13; + reg [0:31] r14; + reg [0:31] r15; + reg [0:31] r16; + + wire valid_o = valid[18]; + + // valid, mode register + always @(posedge clk_i, negedge reset_i) begin + if(~reset_i) begin + valid <= 0; + mode <= 0; + end + else begin + // shift registers + valid[1:18] <= valid[0:17]; + valid[0] <= valid_i; + mode[1:17] <= mode[0:16]; + mode[0] <= mode_i; + end + end + + // des algorithm pipeline + always @(posedge clk_i, negedge reset_i) begin + if(~reset_i) begin + l <= 0; + r <= 0; + l0 <= 0; + l1 <= 0; + l2 <= 0; + l3 <= 0; + l4 <= 0; + l5 <= 0; + l6 <= 0; + l7 <= 0; + l8 <= 0; + l9 <= 0; + l10 <= 0; + l11 <= 0; + l12 <= 0; + l13 <= 0; + l14 <= 0; + l15 <= 0; + l16 <= 0; + r0 <= 0; + r1 <= 0; + r2 <= 0; + r3 <= 0; + r4 <= 0; + r5 <= 0; + r6 <= 0; + r7 <= 0; + r8 <= 0; + r9 <= 0; + r10 <= 0; + r11 <= 0; + r12 <= 0; + r13 <= 0; + r14 <= 0; + r15 <= 0; + r16 <= 0; + data_o <= 0; + end + else begin + // output stage + data_o <= ipn({r16, l16}); + // 16. stage + l16 <= r15; + r16 <= l15 ^ (f(r15, key16)); + // 15. stage + l15 <= r14; + r15 <= l14 ^ (f(r14, key15)); + // 14. stage + l14 <= r13; + r14 <= l13 ^ (f(r13, key14)); + // 13. stage + l13 <= r12; + r13 <= l12 ^ (f(r12, key13)); + // 12. stage + l12 <= r11; + r12 <= l11 ^ (f(r11, key12)); + // 11. stage + l11 <= r10; + r11 <= l10 ^ (f(r10, key11)); + // 10. stage + l10 <= r9; + r10 <= l9 ^ (f(r9, key10)); + // 9. stage + l9 <= r8; + r9 <= l8 ^ (f(r8, key9)); + // 8. stage + l8 <= r7; + r8 <= l7 ^ (f(r7, key8)); + // 7. stage + l7 <= r6; + r7 <= l6 ^ (f(r6, key7)); + // 6. stage + l6 <= r5; + r6 <= l5 ^ (f(r5, key6)); + // 5. stage + l5 <= r4; + r5 <= l4 ^ (f(r4, key5)); + // 4. stage + l4 <= r3; + r4 <= l3 ^ (f(r3, key4)); + // 3. stage + l3 <= r2; + r3 <= l2 ^ (f(r2, key3)); + // 2. stage + l2 <= r1; + r2 <= l1 ^ (f(r1, key2)); + // 1. stage + l1 <= r0; + r1 <= l0 ^ (f(r0, key1)); + // 1. state + l0 <= l; + r0 <= r; + // input stage + l <= ip0(data_i); + r <= ip1(data_i); + end + end + + // des key pipeline + always @(posedge clk_i, negedge reset_i) begin + if(~reset_i) begin + c0 <= 0; + c1 <= 0; + c2 <= 0; + c3 <= 0; + c4 <= 0; + c5 <= 0; + c6 <= 0; + c7 <= 0; + c8 <= 0; + c9 <= 0; + c10 <= 0; + c11 <= 0; + c12 <= 0; + c13 <= 0; + c14 <= 0; + c15 <= 0; + c16 <= 0; + d0 <= 0; + d1 <= 0; + d2 <= 0; + d3 <= 0; + d4 <= 0; + d5 <= 0; + d6 <= 0; + d7 <= 0; + d8 <= 0; + d9 <= 0; + d10 <= 0; + d11 <= 0; + d12 <= 0; + d13 <= 0; + d14 <= 0; + d15 <= 0; + d16 <= 0; + end + else begin + // input stage + c0 <= pc1_c(key_i); + d0 <= pc1_d(key_i); + // 1st stage + if (~mode[0]) begin + c1 <= {c0[1:27], c0[0]}; + d1 <= {d0[1:27], d0[0]}; + end + else begin + c1 <= c0; + d1 <= d0; + end + // 2nd stage + if (~mode[1]) begin + c2 <= {c1[1:27], c1[0]}; + d2 <= {d1[1:27], d1[0]}; + end + else begin + c2 <= {c1[27], c1[0:26]}; + d2 <= {d1[27], d1[0:26]}; + end + // 3rd stage + if (~mode[2]) begin + c3 <= {c2[2:27], c2[0:1]}; + d3 <= {d2[2:27], d2[0:1]}; + end + else begin + c3 <= {c2[26:27], c2[0:25]}; + d3 <= {d2[26:27], d2[0:25]}; + end + // 4th stage + if (~mode[3]) begin + c4 <= {c3[2:27], c3[0:1]}; + d4 <= {d3[2:27], d3[0:1]}; + end + else begin + c4 <= {c3[26:27], c3[0:25]}; + d4 <= {d3[26:27], d3[0:25]}; + end + // 5th stage + if (~mode[4]) begin + c5 <= {c4[2:27], c4[0:1]}; + d5 <= {d4[2:27], d4[0:1]}; + end + else begin + c5 <= {c4[26:27], c4[0:25]}; + d5 <= {d4[26:27], d4[0:25]}; + end + // 6. stage + if (~mode[5]) begin + c6 <= {c5[2:27], c5[0:1]}; + d6 <= {d5[2:27], d5[0:1]}; + end + else begin + c6 <= {c5[26:27], c5[0:25]}; + d6 <= {d5[26:27], d5[0:25]}; + end + // 7. stage + if (~mode[6]) begin + c7 <= {c6[2:27], c6[0:1]}; + d7 <= {d6[2:27], d6[0:1]}; + end + else begin + c7 <= {c6[26:27], c6[0:25]}; + d7 <= {d6[26:27], d6[0:25]}; + end + // 8. stage + if (~mode[7]) begin + c8 <= {c7[2:27], c7[0:1]}; + d8 <= {d7[2:27], d7[0:1]}; + end + else begin + c8 <= {c7[26:27], c7[0:25]}; + d8 <= {d7[26:27], d7[0:25]}; + end + // 9. stage + if (~mode[8]) begin + c9 <= {c8[1:27], c8[0]}; + d9 <= {d8[1:27], d8[0]}; + end + else begin + c9 <= {c8[27], c8[0:26]}; + d9 <= {d8[27], d8[0:26]}; + end + // 10. stage + if (~mode[9]) begin + c10 <= {c9[2:27], c9[0:1]}; + d10 <= {d9[2:27], d9[0:1]}; + end + else begin + c10 <= {c9[26:27], c9[0:25]}; + d10 <= {d9[26:27], d9[0:25]}; + end + // 6. stage + if (~mode[10]) begin + c11 <= {c10[2:27], c10[0:1]}; + d11 <= {d10[2:27], d10[0:1]}; + end + else begin + c11 <= {c10[26:27], c10[0:25]}; + d11 <= {d10[26:27], d10[0:25]}; + end + // 6. stage + if (~mode[11]) begin + c12 <= {c11[2:27], c11[0:1]}; + d12 <= {d11[2:27], d11[0:1]}; + end + else begin + c12 <= {c11[26:27], c11[0:25]}; + d12 <= {d11[26:27], d11[0:25]}; + end + // 6. stage + if (~mode[12]) begin + c13 <= {c12[2:27], c12[0:1]}; + d13 <= {d12[2:27], d12[0:1]}; + end + else begin + c13 <= {c12[26:27], c12[0:25]}; + d13 <= {d12[26:27], d12[0:25]}; + end + // 6. stage + if (~mode[13]) begin + c14 <= {c13[2:27], c13[0:1]}; + d14 <= {d13[2:27], d13[0:1]}; + end + else begin + c14 <= {c13[26:27], c13[0:25]}; + d14 <= {d13[26:27], d13[0:25]}; + end + // 6. stage + if (~mode[14]) begin + c15 <= {c14[2:27], c14[0:1]}; + d15 <= {d14[2:27], d14[0:1]}; + end + else begin + c15 <= {c14[26:27], c14[0:25]}; + d15 <= {d14[26:27], d14[0:25]}; + end + // 6. stage + if (~mode[15]) begin + c16 <= {c15[1:27], c15[0]}; + d16 <= {d15[1:27], d15[0]}; + end + else begin + c16 <= {c15[27], c15[0:26]}; + d16 <= {d15[27], d15[0:26]}; + end + end + end + + // key assignments + assign key1 = pc2({c1, d1}); + assign key2 = pc2({c2, d2}); + assign key3 = pc2({c3, d3}); + assign key4 = pc2({c4, d4}); + assign key5 = pc2({c5, d5}); + assign key6 = pc2({c6, d6}); + assign key7 = pc2({c7, d7}); + assign key8 = pc2({c8, d8}); + assign key9 = pc2({c9, d9}); + assign key10 = pc2({c10, d10}); + assign key11 = pc2({c11, d11}); + assign key12 = pc2({c12, d12}); + assign key13 = pc2({c13, d13}); + assign key14 = pc2({c14, d14}); + assign key15 = pc2({c15, d15}); + assign key16 = pc2({c16, d16}); + + +endmodule + + + + diff --git a/tdes/rtl/verilog/des_pkg.v b/tdes/rtl/verilog/des_pkg.v new file mode 100644 index 0000000..f887bed --- /dev/null +++ b/tdes/rtl/verilog/des_pkg.v @@ -0,0 +1,246 @@ +// ====================================================================== +// DES encryption/decryption +// package file with functions +// Copyright (C) 2012 Torsten Meissner +//----------------------------------------------------------------------- +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +// ====================================================================== + + +function [0:31] ip0 (input [0:63] data); +begin + ip0 = {data[57], data[49], data[41], data[33], data[25], data[17], data[ 9], data[1], + data[59], data[51], data[43], data[35], data[27], data[19], data[11], data[3], + data[61], data[53], data[45], data[37], data[29], data[21], data[13], data[5], + data[63], data[55], data[47], data[39], data[31], data[23], data[15], data[7]}; +end +endfunction + + +function [0:31] ip1 (input [0:63] data); +begin + ip1 = {data[56], data[48], data[40], data[32], data[24], data[16], data[ 8], data[0], + data[58], data[50], data[42], data[34], data[26], data[18], data[10], data[2], + data[60], data[52], data[44], data[36], data[28], data[20], data[12], data[4], + data[62], data[54], data[46], data[38], data[30], data[22], data[14], data[6]}; +end +endfunction + + +function [0:63] ipn (input [0:63] data); +begin + ipn = {data[39], data[7], data[47], data[15], data[55], data[23], data[63], data[31], + data[38], data[6], data[46], data[14], data[54], data[22], data[62], data[30], + data[37], data[5], data[45], data[13], data[53], data[21], data[61], data[29], + data[36], data[4], data[44], data[12], data[52], data[20], data[60], data[28], + data[35], data[3], data[43], data[11], data[51], data[19], data[59], data[27], + data[34], data[2], data[42], data[10], data[50], data[18], data[58], data[26], + data[33], data[1], data[41], data[ 9], data[49], data[17], data[57], data[25], + data[32], data[0], data[40], data[ 8], data[48], data[16], data[56], data[24]}; +end +endfunction + + +function [0:47] e (input [0:31] data); +begin + e = {data[31], data[ 0], data[ 1], data[ 2], data[ 3], data[ 4], + data[ 3], data[ 4], data[ 5], data[ 6], data[ 7], data[ 8], + data[ 7], data[ 8], data[ 9], data[10], data[11], data[12], + data[11], data[12], data[13], data[14], data[15], data[16], + data[15], data[16], data[17], data[18], data[19], data[20], + data[19], data[20], data[21], data[22], data[23], data[24], + data[23], data[24], data[25], data[26], data[27], data[28], + data[27], data[28], data[29], data[30], data[31], data[ 0]}; +end +endfunction + + +function [0:3] s1 (input [0:5] data); + reg [0:255] matrix; + integer pos; + integer index; +begin + matrix = 256'hE4D12FB83A6C5907_0F74E2D1A6CB9538_41E8D62BFC973A50_FC8249175B3EA06D; + pos = {data[0], data[5]} * 64 + data[1:4] * 4; + for(index = 0 ; index <= 3; index = index + 1) + begin + s1[index] = matrix[pos + index]; + end +end +endfunction + + +function [0:3] s2 (input [0:5] data); + reg [0:255] matrix; + integer pos; + integer index; +begin + matrix = 256'hF18E6B34972DC05A_3D47F28EC01A69B5_0E7BA4D158C6932F_D8A13F42B67C05E9; + pos = {data[0], data[5]} * 64 + data[1:4] * 4; + for(index = 0 ; index <= 3; index = index + 1) + begin + s2[index] = matrix[pos + index]; + end +end +endfunction + + +function [0:3] s3 (input [0:5] data); + reg [0:255] matrix; + integer pos; + integer index; +begin + matrix = 256'hA09E63F51DC7B428_D709346A285ECBF1_D6498F30B12C5AE7_1AD069874FE3B52C; + pos = {data[0], data[5]} * 64 + data[1:4] * 4; + for(index = 0 ; index <= 3; index = index + 1) + begin + s3[index] = matrix[pos + index]; + end +end +endfunction + + +function [0:3] s4 (input [0:5] data); + reg [0:255] matrix; + integer pos; + integer index; +begin + matrix = 256'h7DE3069A1285BC4F_D8B56F03472C1AE9_A690CB7DF13E5284_3F06A1D8945BC72E; + pos = {data[0], data[5]} * 64 + data[1:4] * 4; + for(index = 0 ; index <= 3; index = index + 1) + begin + s4[index] = matrix[pos + index]; + end +end +endfunction + + +function [0:3] s5 (input [0:5] data); + reg [0:255] matrix; + integer pos; + integer index; +begin + matrix = 256'h2C417AB6853FD0E9_EB2C47D150FA3986_421BAD78F9C5630E_B8C71E2D6F09A453; + pos = {data[0], data[5]} * 64 + data[1:4] * 4; + for(index = 0 ; index <= 3; index = index + 1) + begin + s5[index] = matrix[pos + index]; + end +end +endfunction + + +function [0:3] s6 (input [0:5] data); + reg [0:255] matrix; + integer pos; + integer index; +begin + matrix = 256'hC1AF92680D34E75B_AF427C9561DE0B38_9EF528C3704A1DB6_432C95FABE17608D; + pos = {data[0], data[5]} * 64 + data[1:4] * 4; + for(index = 0 ; index <= 3; index = index + 1) + begin + s6[index] = matrix[pos + index]; + end +end +endfunction + + +function [0:3] s7 (input [0:5] data); + reg [0:255] matrix; + integer pos; + integer index; +begin + matrix = 256'h4B2EF08D3C975A61_D0B7491AE35C2F86_14BDC37EAF680592_6BD814A7950FE23C; + pos = {data[0], data[5]} * 64 + data[1:4] * 4; + for(index = 0 ; index <= 3; index = index + 1) + begin + s7[index] = matrix[pos + index]; + end +end +endfunction + + +function [0:3] s8 (input [0:5] data); + reg [0:255] matrix; + integer pos; + integer index; +begin + matrix = 256'hD2846FB1A93E50C7_1FD8A374C56B0E92_7B419CE206ADF358_21E74A8DFC90356B; + pos = {data[0], data[5]} * 64 + data[1:4] * 4; + for(index = 0 ; index <= 3; index = index + 1) + begin + s8[index] = matrix[pos + index]; + end +end +endfunction + + +function [0:31] p (input [0:31] data); +begin + p = {data[15], data[ 6], data[19], data[20], + data[28], data[11], data[27], data[16], + data[ 0], data[14], data[22], data[25], + data[ 4], data[17], data[30], data[ 9], + data[ 1], data[ 7], data[23], data[13], + data[31], data[26], data[ 2], data[ 8], + data[18], data[12], data[29], data[ 5], + data[21], data[10], data[ 3], data[24]}; +end +endfunction + + +function [0:31] f (input [0:31] data, input [0:47] key); + reg [0:47] intern; +begin + intern = e(data) ^ key; + f = p({s1(intern[0:5]), s2(intern[6:11]), s3(intern[12:17]), s4(intern[18:23]), + s5(intern[24:29]), s6(intern[30:35]), s7(intern[36:41]), s8(intern[42:47])}); +end +endfunction + + +function [0:27] pc1_c (input [0:63] data); +begin + pc1_c = {data[56], data[48], data[40], data[32], data[24], data[16], data[ 8], + data[ 0], data[57], data[49], data[41], data[33], data[25], data[17], + data[ 9], data[ 1], data[58], data[50], data[42], data[34], data[26], + data[18], data[10], data[ 2], data[59], data[51], data[43], data[35]}; +end +endfunction + + +function [0:27] pc1_d (input [0:63] data); +begin + pc1_d = {data[62], data[54], data[46], data[38], data[30], data[22], data[14], + data[ 6], data[61], data[53], data[45], data[37], data[29], data[21], + data[13], data[ 5], data[60], data[52], data[44], data[36], data[28], + data[20], data[12], data[ 4], data[27], data[19], data[11], data[ 3]}; +end +endfunction + + +function [0:47] pc2 (input [0:55] data); +begin + pc2 = {data[13], data[16], data[10], data[23], data[ 0], data[ 4], + data[ 2], data[27], data[14], data[ 5], data[20], data[ 9], + data[22], data[18], data[11], data[ 3], data[25], data[ 7], + data[15], data[ 6], data[26], data[19], data[12], data[ 1], + data[40], data[51], data[30], data[36], data[46], data[54], + data[29], data[39], data[50], data[44], data[32], data[47], + data[43], data[48], data[38], data[55], data[33], data[52], + data[45], data[41], data[49], data[35], data[28], data[31]}; +end +endfunction + From e2225fbbc9b98d1231232703590e8cfe3eb8b7d3 Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Sun, 24 Mar 2013 16:37:16 +0100 Subject: [PATCH 8/8] initial commit os TDES verilog design file --- tdes/rtl/verilog/tdes.v | 129 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 tdes/rtl/verilog/tdes.v diff --git a/tdes/rtl/verilog/tdes.v b/tdes/rtl/verilog/tdes.v new file mode 100644 index 0000000..76ff2a8 --- /dev/null +++ b/tdes/rtl/verilog/tdes.v @@ -0,0 +1,129 @@ +// ====================================================================== +// TDES encryption/decryption +// algorithm according:FIPS 46-3 specification +// Copyright (C) 2012 Torsten Meissner +//----------------------------------------------------------------------- +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write:the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +// ====================================================================== + + +`timescale 1ns/1ps + + +module tdes + ( + input reset_i, // async reset + input clk_i, // clock + input mode_i, // des-mode: 0 = encrypt, 1 = decrypt + input [0:63] key1_i, // key input + input [0:63] key2_i // key input + input [0:63] key3_i // key input + input [0:63] data_i, // data input + input valid_i, // input key/data valid flag + output reg [0:63] data_o, // data output + output valid_o, // output data valid flag + output reg ready_o // ready for new data + ); + + +`include "../../rtl/verilog/des.v" + + + reg reset; + reg mode; + reg [0:63] key1; + reg [0:63] key2; + reg [0:63] key3; + reg ready_o; + + + + // input register + always @(posedge clk_i, negedge reset_i) begin + if (~reset_i) begin + reset <= 0; + mode <= 0; + key1 <= 0; + key2 <= 0; + key3 <= 0; + end + else begin + reset <= reset_i; + if (valid_i && ready_o) begin + mode <= mode_i; + key1 <= key1_i; + key2 <= key2_i; + key3 <= key3_i; + end + end + end + + + // output register + always @(posedge clk_i, negedge reset_i) begin + if (~reset_i) begin + ready_o <= 0; + end + else begin + if (valid_i && ready_o) begin + ready_o <= 0; + end + if (valid_o || (reset_i && ~reset)) begin + ready_o <= 1; + end + end + end + + + des : i1_des + ( + .reset_i(reset_i), + .clk_i(clk_i), + .mode_i(mode_i), + .key_i(des1_key), + .data_i(data_i), + .valid_i(des1_validin), + .data_o(des1_dataout), + .valid_o(des1_validout) + ); + + + des : i2_des + ( + .reset_i(reset_i), + .clk_i(clk_i), + .mode_i(des2_mode), + .key_i(key2), + .data_i(des1_dataout), + .valid_i(des1_validout), + .data_o(des2_dataout), + .valid_o(des2_validout) + ); + + + des : i3_des + ( + .reset_i(reset_i), + .clk_i(clk_i), + .mode_i(mode_i), + .key_i(des1_key), + .data_i(des2_dataout), + .valid_i(des2_validout), + .data_o(data_o), + .valid_o(valid_o) + ); + + +endmodule