diff --git a/cbcdes/rtl/vhdl/cbcdes.vhd b/cbcdes/rtl/vhdl/cbcdes.vhd
index 518a4f1..5ef1feb 100644
--- a/cbcdes/rtl/vhdl/cbcdes.vhd
+++ b/cbcdes/rtl/vhdl/cbcdes.vhd
@@ -37,13 +37,14 @@ entity cbcdes is
     clk_i       : in  std_logic;                  -- clock
     start_i     : in  std_logic;                  -- start cbc
     mode_i      : in  std_logic;                  -- des-modus: 0 = encrypt, 1 = decrypt
-    key_i       : in  std_logic_vector(0 TO 63);  -- key input
+    key_i       : in  std_logic_vector(0 to 63);  -- key input
     iv_i        : in  std_logic_vector(0 to 63);  -- iv input
-    data_i      : in  std_logic_vector(0 TO 63);  -- data input
+    data_i      : in  std_logic_vector(0 to 63);  -- data input
     valid_i     : in  std_logic;                  -- input key/data valid flag
-    ready_o     : out std_logic;                  -- ready to encrypt/decrypt
-    data_o      : out std_logic_vector(0 TO 63);  -- data output
-    valid_o     : out std_logic                   -- output data valid flag
+    accept_o    : out std_logic;                  -- ready to encrypt/decrypt
+    data_o      : out std_logic_vector(0 to 63);  -- data output
+    valid_o     : out std_logic;                   -- output data valid flag
+    accept_i    : in  std_logic
   );
 end entity cbcdes;
 
@@ -51,20 +52,6 @@ end entity cbcdes;
 architecture rtl of cbcdes is
 
 
-  component des is
-    port (
-      reset_i     : in  std_logic;
-      clk_i       : IN  std_logic;                  -- clock
-      mode_i      : IN  std_logic;                  -- des-modus: 0 = encrypt, 1 = decrypt
-      key_i       : IN  std_logic_vector(0 TO 63);  -- key input
-      data_i      : IN  std_logic_vector(0 TO 63);  -- data input
-      valid_i     : IN  std_logic;                  -- input key/data valid flag
-      data_o      : OUT std_logic_vector(0 TO 63);  -- data output
-      valid_o     : OUT std_logic                   -- output data valid flag
-    );
-  end component des;
- 
-
   signal s_mode       : std_logic;
   signal s_des_mode   : std_logic;
   signal s_start      : std_logic;
@@ -74,83 +61,71 @@ architecture rtl of cbcdes is
   signal s_datain     : std_logic_vector(0 to 63);
   signal s_datain_d   : std_logic_vector(0 to 63);
   signal s_des_datain : std_logic_vector(0 to 63);
-  signal s_validin    : std_logic;
   signal s_des_dataout : std_logic_vector(0 to 63);
   signal s_dataout    : std_logic_vector(0 to 63);
-  signal s_validout   : std_logic;
-  signal s_ready      : std_logic;
-  signal s_reset      : std_logic;
- 
+
 
 begin
 
 
-  s_des_datain <= iv_i xor data_i      when mode_i = '0' and start_i = '1' else
+  s_des_datain <= iv_i      xor data_i when mode_i = '0' and start_i = '1' else
                   s_dataout xor data_i when s_mode = '0' and start_i = '0' else
                   data_i;
-  data_o       <= s_iv xor s_des_dataout     when s_mode = '1' and s_start = '1' else
+  data_o       <= s_iv       xor s_des_dataout when s_mode = '1' and s_start = '1' else
                   s_datain_d xor s_des_dataout when s_mode = '1' and s_start = '0' else
                   s_des_dataout;
   s_des_key    <= key_i  when start_i = '1' else s_key;
   s_des_mode   <= mode_i when start_i = '1' else s_mode;
 
-  ready_o     <= s_ready;
-  s_validin   <= valid_i and s_ready;
-  valid_o     <= s_validout;
 
-  inputregister : process(clk_i, reset_i) is
+  inputregister : process (clk_i, reset_i) is
   begin
-    if(reset_i = '0') then
-      s_reset    <= '0';
+    if (reset_i = '0') then
       s_mode     <= '0';
       s_start    <= '0';
       s_key      <= (others => '0');
       s_iv       <= (others => '0');
       s_datain   <= (others => '0');
       s_datain_d <= (others => '0');
-    elsif(rising_edge(clk_i)) then
-      s_reset  <= reset_i;
-      if(valid_i = '1' and s_ready = '1') then
-        s_start  <= start_i;
+    elsif (rising_edge(clk_i)) then
+      if (valid_i = '1' and accept_o = '1') then
+        s_start    <= start_i;
         s_datain   <= data_i;
         s_datain_d <= s_datain;
-      end if;
-      if(valid_i = '1' and s_ready = '1' and start_i = '1') then
-        s_mode   <= mode_i;
-        s_key    <= key_i;
-        s_iv     <= iv_i;
+        if (start_i = '1') then
+          s_mode <= mode_i;
+          s_key  <= key_i;
+          s_iv   <= iv_i;
+        end if;
       end if;
     end if;
   end process inputregister;
 
 
-  outputregister : process(clk_i, reset_i) is
+  outputregister : process (clk_i, reset_i) is
   begin
-    if(reset_i = '0') then
-      s_ready   <= '0';
+    if (reset_i = '0') then
       s_dataout <= (others => '0');
-    elsif(rising_edge(clk_i)) then
-      if(valid_i = '1' and s_ready = '1') then
-        s_ready <= '0';
-      end if;
-      if(s_validout = '1' or (reset_i = '1' and s_reset = '0')) then
-        s_ready   <= '1';
+    elsif (rising_edge(clk_i)) then
+      if (valid_o = '1' and accept_i = '1') then
         s_dataout <= s_des_dataout;
       end if;
     end if;
   end process outputregister;
-      
 
-  i_des : des
+
+  i_des : entity work.des
     port map (
-      reset_i => s_reset,
-      clk_i   => clk_i,
-      mode_i  => s_des_mode,
-      key_i   => s_des_key,
-      data_i  => s_des_datain,
-      valid_i => s_validin,
-      data_o  => s_des_dataout,
-      valid_o => s_validout
+      reset_i  => reset_i,
+      clk_i    => clk_i,
+      mode_i   => s_des_mode,
+      key_i    => s_des_key,
+      data_i   => s_des_datain,
+      valid_i  => valid_i,
+      accept_o => accept_o,
+      data_o   => s_des_dataout,
+      valid_o  => valid_o,
+      accept_i => accept_i
     );
 
 
diff --git a/cbcdes/rtl/vhdl/des.vhd b/cbcdes/rtl/vhdl/des.vhd
deleted file mode 100644
index 9ebc905..0000000
--- a/cbcdes/rtl/vhdl/des.vhd
+++ /dev/null
@@ -1,340 +0,0 @@
--- ======================================================================
--- DES encryption/decryption
--- algorithm according to FIPS 46-3 specification
--- Copyright (C) 2007 Torsten Meissner
--------------------------------------------------------------------------
--- This program is free software; you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation; either version 2 of the License, or
--- (at your option) any later version.
-
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
-
--- You should have received a copy of the GNU General Public License
--- along with this program; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
--- ======================================================================
-
-
--- Revision 1.0  2007/02/04
--- Initial release
--- Revision 1.1  2007/02/05
--- Corrected error in use of mode register for key calculation
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-USE ieee.numeric_std.ALL;
-USE work.des_pkg.ALL;
-
-
-ENTITY des IS
-  PORT (
-    reset_i     : in  std_logic;                  -- async reset
-    clk_i       : IN  std_logic;                  -- clock
-    mode_i      : IN  std_logic;                  -- des-modus: 0 = encrypt, 1 = decrypt
-    key_i       : IN  std_logic_vector(0 TO 63);  -- key input
-    data_i      : IN  std_logic_vector(0 TO 63);  -- data input
-    valid_i     : IN  std_logic;                  -- input key/data valid flag
-    data_o      : OUT std_logic_vector(0 TO 63);  -- data output
-    valid_o     : OUT std_logic                   -- output data valid flag
-  );
-END ENTITY des;
-
-
-ARCHITECTURE rtl OF des IS
-
-BEGIN
-
-  crypt : PROCESS ( clk_i ) IS
-    -- variables for key calculation
-    VARIABLE c0  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c1  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c2  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c3  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c4  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c5  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c6  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c7  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c8  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c9  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d0  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d1  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d2  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d3  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d4  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d5  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d6  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d7  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d8  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d9  : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0');
-    VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0');
-    -- key variables
-    VARIABLE key1  : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key2  : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key3  : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key4  : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key5  : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key6  : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key7  : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key8  : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key9  : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0');
-    VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0');
-    -- variables for left & right data blocks
-    VARIABLE l0  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l1  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l2  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l3  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l4  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l5  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l6  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l7  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l8  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l9  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r0  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r1  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r2  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r3  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r4  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r5  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r6  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r7  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r8  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r9  : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0');
-    VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0');
-    -- variables for mode & valid shift registers
-    VARIABLE mode  : std_logic_vector(0 TO 16) := (others => '0');
-    VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0');
-  BEGIN
-    if(reset_i = '0') then
-      data_o  <= (others => '0');
-      valid_o <= '0';
-    elsif rising_edge( clk_i ) THEN
-      -- shift registers
-      valid(1 TO 17) := valid(0 TO 16);
-      valid(0) := valid_i;
-      mode(1 TO 16) := mode(0 TO 15);
-      mode(0)  := mode_i;
-      -- output stage
-      valid_o <= valid(17);
-      data_o  <= ipn( ( r16 & l16 ) );
-      -- 16. stage
-      IF mode(16) = '0' THEN
-        c16 := c15(1 TO 27) & c15(0);
-        d16 := d15(1 TO 27) & d15(0);
-      ELSE
-        c16 := c15(27) & c15(0 TO 26);
-        d16 := d15(27) & d15(0 TO 26);
-      END IF;
-      key16 := pc2( ( c16 & d16 ) );
-      l16 := r15;
-      r16 := l15 xor ( f( r15, key16 ) );
-      -- 15. stage
-      IF mode(15) = '0' THEN
-        c15 := c14(2 TO 27) & c14(0 TO 1);
-        d15 := d14(2 TO 27) & d14(0 TO 1);
-      ELSE
-        c15 := c14(26 TO 27) & c14(0 TO 25);
-        d15 := d14(26 TO 27) & d14(0 TO 25);
-      END IF;
-      key15 := pc2( ( c15 & d15 ) );
-      l15 := r14;
-      r15 := l14 xor ( f( r14, key15 ) );
-      -- 14. stage
-      IF mode(14) = '0' THEN
-        c14 := c13(2 TO 27) & c13(0 TO 1);
-        d14 := d13(2 TO 27) & d13(0 TO 1);
-      ELSE
-        c14 := c13(26 TO 27) & c13(0 TO 25);
-        d14 := d13(26 TO 27) & d13(0 TO 25);
-      END IF;
-      key14 := pc2( ( c14 & d14 ) );
-      l14 := r13;
-      r14 := l13 xor ( f( r13, key14 ) );
-      -- 13. stage
-      IF mode(13) = '0' THEN
-        c13 := c12(2 TO 27) & c12(0 TO 1);
-        d13 := d12(2 TO 27) & d12(0 TO 1);
-      ELSE
-        c13 := c12(26 TO 27) & c12(0 TO 25);
-        d13 := d12(26 TO 27) & d12(0 TO 25);
-      END IF;
-      key13 := pc2( ( c13 & d13 ) );
-      l13 := r12;
-      r13 := l12 xor ( f( r12, key13 ) );
-      -- 12. stage
-      IF mode(12) = '0' THEN
-        c12 := c11(2 TO 27) & c11(0 TO 1);
-        d12 := d11(2 TO 27) & d11(0 TO 1);
-      ELSE
-        c12 := c11(26 TO 27) & c11(0 TO 25);
-        d12 := d11(26 TO 27) & d11(0 TO 25);
-      END IF;
-      key12 := pc2( ( c12 & d12 ) );
-      l12 := r11;
-      r12 := l11 xor ( f( r11, key12 ) );
-      -- 11. stage
-      IF mode(11) = '0' THEN
-        c11 := c10(2 TO 27) & c10(0 TO 1);
-        d11 := d10(2 TO 27) & d10(0 TO 1);
-      ELSE
-        c11 := c10(26 TO 27) & c10(0 TO 25);
-        d11 := d10(26 TO 27) & d10(0 TO 25);
-      END IF;
-      key11 := pc2( ( c11 & d11 ) );
-      l11 := r10;
-      r11 := l10 xor ( f( r10, key11 ) );
-      -- 10. stage
-      IF mode(10) = '0' THEN
-        c10 := c9(2 TO 27) & c9(0 TO 1);
-        d10 := d9(2 TO 27) & d9(0 TO 1);
-      ELSE
-        c10 := c9(26 TO 27) & c9(0 TO 25);
-        d10 := d9(26 TO 27) & d9(0 TO 25);
-      END IF;
-      key10 := pc2( ( c10 & d10 ) );
-      l10 := r9;
-      r10 := l9 xor ( f( r9, key10 ) );
-      -- 9. stage
-      IF mode(9) = '0' THEN
-        c9 := c8(1 TO 27) & c8(0);
-        d9 := d8(1 TO 27) & d8(0);
-      ELSE
-        c9 := c8(27) & c8(0 TO 26);
-        d9 := d8(27) & d8(0 TO 26);
-      END IF;
-      key9 := pc2( ( c9 & d9 ) );
-      l9 := r8;
-      r9 := l8 xor ( f( r8, key9 ) );
-      -- 8. stage
-      IF mode(8) = '0' THEN
-        c8 := c7(2 TO 27) & c7(0 TO 1);
-        d8 := d7(2 TO 27) & d7(0 TO 1);
-      ELSE
-        c8 := c7(26 TO 27) & c7(0 TO 25);
-        d8 := d7(26 TO 27) & d7(0 TO 25);
-      END IF;
-      key8 := pc2( ( c8 & d8 ) );
-      l8 := r7;
-      r8 := l7 xor ( f( r7, key8 ) );
-      -- 7. stage
-      IF mode(7) = '0' THEN
-        c7 := c6(2 TO 27) & c6(0 TO 1);
-        d7 := d6(2 TO 27) & d6(0 TO 1);
-      ELSE
-        c7 := c6(26 TO 27) & c6(0 TO 25);
-        d7 := d6(26 TO 27) & d6(0 TO 25);
-      END IF;
-      key7 := pc2( ( c7 & d7 ) );
-      l7 := r6;
-      r7 := l6 xor ( f( r6, key7 ) );
-      -- 6. stage
-      IF mode(6) = '0' THEN
-        c6 := c5(2 TO 27) & c5(0 TO 1);
-        d6 := d5(2 TO 27) & d5(0 TO 1);
-      ELSE
-        c6 := c5(26 TO 27) & c5(0 TO 25);
-        d6 := d5(26 TO 27) & d5(0 TO 25);
-      END IF;
-      key6 := pc2( ( c6 & d6 ) );
-      l6 := r5;
-      r6 := l5 xor ( f( r5, key6 ) );
-      -- 5. stage
-      IF mode(5) = '0' THEN
-        c5 := c4(2 TO 27) & c4(0 TO 1);
-        d5 := d4(2 TO 27) & d4(0 TO 1);
-      ELSE
-        c5 := c4(26 TO 27) & c4(0 TO 25);
-        d5 := d4(26 TO 27) & d4(0 TO 25);
-      END IF;
-      key5 := pc2( ( c5 & d5 ) );
-      l5 := r4;
-      r5 := l4 xor ( f( r4, key5 ) );
-      -- 4. stage
-      IF mode(4) = '0' THEN
-        c4 := c3(2 TO 27) & c3(0 TO 1);
-        d4 := d3(2 TO 27) & d3(0 TO 1);
-      ELSE
-        c4 := c3(26 TO 27) & c3(0 TO 25);
-        d4 := d3(26 TO 27) & d3(0 TO 25);
-      END IF;
-      key4 := pc2( ( c4 & d4 ) );
-      l4 := r3;
-      r4 := l3 xor ( f( r3, key4 ) );
-      -- 3. stage
-      IF mode(3) = '0' THEN
-        c3 := c2(2 TO 27) & c2(0 TO 1);
-        d3 := d2(2 TO 27) & d2(0 TO 1);
-      ELSE
-        c3 := c2(26 TO 27) & c2(0 TO 25);
-        d3 := d2(26 TO 27) & d2(0 TO 25);
-      END IF;
-      key3 := pc2( ( c3 & d3 ) );
-      l3 := r2;
-      r3 := l2 xor ( f( r2, key3 ) );
-      -- 2. stage
-      IF mode(2) = '0' THEN
-        c2 := c1(1 TO 27) & c1(0);
-        d2 := d1(1 TO 27) & d1(0);
-      ELSE
-        c2 := c1(27) & c1(0 TO 26);
-        d2 := d1(27) & d1(0 TO 26);
-      END IF;
-      key2 := pc2( ( c2 & d2 ) );
-      l2 := r1;
-      r2 := l1 xor ( f( r1, key2 ) );
-      -- 1. stage
-      IF mode(1) = '0' THEN
-        c1 := c0(1 TO 27) & c0(0);
-        d1 := d0(1 TO 27) & d0(0);
-      ELSE
-        c1 := c0;
-        d1 := d0;
-      END IF;
-      key1 := pc2( ( c1 & d1 ) );
-      l1 := r0;
-      r1 := l0 xor ( f( r0, key1 ) );
-      -- input stage
-      l0 := ip( data_i )(0 TO 31);
-      r0 := ip( data_i )(32 TO 63);
-      c0 := pc1_c( key_i );
-      d0 := pc1_d( key_i );
-    END IF;
-  END PROCESS crypt;
-
-END ARCHITECTURE rtl;
diff --git a/cbcdes/rtl/vhdl/des_pkg.vhd b/cbcdes/rtl/vhdl/des_pkg.vhd
deleted file mode 100644
index 220704e..0000000
--- a/cbcdes/rtl/vhdl/des_pkg.vhd
+++ /dev/null
@@ -1,336 +0,0 @@
--- ======================================================================
--- DES encryption/decryption
--- package file with functions
--- Copyright (C) 2007 Torsten Meissner
--------------------------------------------------------------------------
--- This program is free software; you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation; either version 2 of the License, or
--- (at your option) any later version.
-
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
-
--- You should have received a copy of the GNU General Public License
--- along with this program; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
--- ======================================================================
-
-
--- Revision 1.0  2007/02/04
--- Initial release
-
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-USE ieee.numeric_std.ALL;
-
-
-
-PACKAGE des_pkg IS
-
-
-  FUNCTION ip  ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
-  FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
-
-  FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
-  FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
-
-  FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
-  FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
-  FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
-  FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
-  FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
-  FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
-  FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
-  FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
-
-  FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector;
-
-  FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
-  FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
-  FUNCTION pc2   ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector;
-
-  TYPE ip_matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63;
-  constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17,  9, 1,
-                                59, 51, 43, 35, 27, 19, 11, 3,
-                                61, 53, 45, 37, 29, 21, 13, 5,
-                                63, 55, 47, 39, 31, 23, 15, 7,
-                                56, 48, 40, 32, 24, 16,  8, 0,
-                                58, 50, 42, 34, 26, 18, 10, 2,
-                                60, 52, 44, 36, 28, 20, 12, 4,
-                                62, 54, 46, 38, 30, 22, 14, 6);
-  constant ipn_table : ip_matrix := (39,  7, 47, 15, 55, 23, 63, 31,
-                                38,  6, 46, 14, 54, 22, 62, 30,
-                                37,  5, 45, 13, 53, 21, 61, 29,
-                                36,  4, 44, 12, 52, 20, 60, 28,
-                                35,  3, 43, 11, 51, 19, 59, 27,
-                                34,  2, 42, 10, 50, 18, 58, 26,
-                                33,  1, 41,  9, 49, 17, 57, 25,
-                                32,  0, 40,  8, 48, 16, 56, 24);
-
-  TYPE e_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31;
-  constant e_table : e_matrix := (31,  0,  1,  2,  3,  4,
-                                 3,  4,  5,  6,  7,  8,
-                                 7,  8,  9, 10, 11, 12,
-                                11, 12, 13, 14, 15, 16,
-                                15, 16, 17, 18, 19, 20,
-                                19, 20, 21, 22, 23, 24,
-                                23, 24, 25, 26, 27, 28,
-                                27, 28, 29, 30, 31,  0);
-
-  TYPE s_matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15;
-  constant s1_table  : s_matrix := (0 => (14,  4, 13,  1,  2, 15, 11,  8,  3, 10,  6, 12,  5,  9,  0,  7),
-                                    1 => ( 0, 15,  7,  4, 14,  2, 13,  1, 10,  6, 12, 11,  9,  5,  3,  8),
-                                    2 => ( 4,  1, 14,  8, 13,  6,  2, 11, 15, 12,  9,  7,  3, 10,  5,  0),
-                                    3 => (15, 12,  8,  2,  4,  9,  1,  7,  5, 11,  3, 14, 10,  0,  6, 13));
-  constant s2_table  : s_matrix := (0 => (15,  1,  8, 14,  6, 11,  3,  4,  9,  7,  2, 13, 12,  0,  5, 10),
-                                    1 => ( 3, 13,  4,  7, 15,  2,  8, 14, 12,  0,  1, 10,  6,  9, 11,  5),
-                                    2 => ( 0, 14,  7, 11, 10,  4, 13,  1,  5,  8, 12,  6,  9,  3,  2, 15),
-                                    3 => (13,  8, 10,  1,  3, 15,  4,  2, 11,  6,  7, 12,  0,  5, 14,  9));
-  constant s3_table  : s_matrix := (0 => (10,  0,  9, 14,  6,  3, 15,  5,  1, 13, 12,  7, 11,  4,  2,  8),
-                                    1 => (13,  7,  0,  9,  3,  4,  6, 10,  2,  8,  5, 14, 12, 11, 15,  1),
-                                    2 => (13,  6,  4,  9,  8, 15,  3,  0, 11,  1,  2, 12,  5, 10, 14,  7),
-                                    3 => ( 1, 10, 13,  0,  6,  9,  8,  7,  4, 15, 14,  3, 11,  5,  2, 12));
-  constant s4_table  : s_matrix := (0 => ( 7, 13, 14,  3,  0,  6,  9, 10,  1,  2,  8,  5, 11, 12,  4,  15),
-                                    1 => (13,  8, 11,  5,  6, 15,  0,  3,  4,  7,  2, 12,  1, 10, 14,   9),
-                                    2 => (10,  6,  9,  0, 12, 11,  7, 13, 15,  1,  3, 14,  5,  2,  8,   4),
-                                    3 => ( 3, 15,  0,  6, 10,  1, 13,  8,  9,  4,  5, 11, 12,  7,  2,  14));
-  constant s5_table  : s_matrix := (0 => ( 2, 12,  4,  1,  7, 10, 11,  6,  8,  5,  3, 15, 13,  0, 14,  9),
-                                    1 => (14, 11,  2, 12,  4,  7, 13,  1,  5,  0, 15, 10,  3,  9,  8,  6),
-                                    2 => ( 4,  2,  1, 11, 10, 13,  7,  8, 15,  9, 12,  5,  6,  3,  0, 14),
-                                    3 => (11,  8, 12,  7,  1, 14,  2, 13,  6, 15,  0,  9, 10,  4,  5,  3));
-  constant s6_table  : s_matrix := (0 => (12,  1, 10, 15,  9,  2,  6,  8,  0, 13,  3,  4, 14,  7,  5, 11),
-                                    1 => (10, 15,  4,  2,  7, 12,  9,  5,  6,  1, 13, 14,  0, 11,  3,  8),
-                                    2 => ( 9, 14, 15,  5,  2,  8, 12,  3,  7,  0,  4, 10,  1, 13, 11,  6),
-                                    3 => ( 4,  3,  2, 12,  9,  5, 15, 10, 11, 14,  1,  7,  6,  0,  8, 13));
-  constant s7_table  : s_matrix := (0 => ( 4, 11,  2, 14, 15,  0,  8, 13,  3, 12,  9,  7,  5, 10,  6,  1),
-                                    1 => (13,  0, 11,  7,  4,  9,  1, 10, 14,  3,  5, 12,  2, 15,  8,  6),
-                                    2 => ( 1,  4, 11, 13, 12,  3,  7, 14, 10, 15,  6,  8,  0,  5,  9,  2),
-                                    3 => ( 6, 11, 13,  8,  1,  4, 10,  7,  9,  5,  0, 15, 14,  2,  3, 12));
-  constant s8_table  : s_matrix := (0 => (13,  2,  8,  4,  6, 15, 11,  1, 10,  9,  3, 14,  5,  0, 12,  7),
-                                    1 => ( 1, 15, 13,  8, 10,  3,  7,  4, 12,  5,  6, 11,  0, 14,  9,  2),
-                                    2 => ( 7, 11,  4,  1,  9, 12, 14,  2,  0,  6, 10, 13, 15,  3,  5,  8),
-                                    3 => ( 2,  1, 14,  7,  4, 10,  8, 13, 15, 12,  9,  0,  3,  5,  6, 11));
-
-  type pc_matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63;
-  constant pc1c_table : pc_matrix := (56, 48, 40, 32, 24, 16,  8,
-                                 0, 57, 49, 41, 33, 25, 17,
-                                 9,  1, 58, 50, 42, 34, 26,
-                                18, 10,  2, 59, 51, 43, 35);
-  constant pc1d_table : pc_matrix := (62, 54, 46, 38, 30, 22, 14,
-                                 6, 61, 53, 45, 37, 29, 21,
-                                13,  5, 60, 52, 44, 36, 28,
-                                20, 12,  4, 27, 19, 11,  3);
-
-  type p_matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31;
-  constant p_table : p_matrix := (15,  6, 19, 20,
-                                28, 11, 27, 16,
-                                 0, 14, 22, 25,
-                                 4, 17, 30,  9,
-                                 1,  7, 23, 13,
-                                31, 26,  2,  8,
-                                18, 12, 29,  5,
-                                21, 10,  3, 24);
-
-  type pc2_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63;
-  constant pc2_table : pc2_matrix := (13, 16, 10, 23,  0,  4,
-                                 2, 27, 14,  5, 20,  9,
-                                22, 18, 11,  3, 25,  7,
-                                15,  6, 26, 19, 12,  1,
-                                40, 51, 30, 36, 46, 54,
-                                29, 39, 50, 44, 32, 47,
-                                43, 48, 38, 55, 33, 52,
-                                45, 41, 49, 35, 28, 31);
-
-
-END PACKAGE des_pkg;
-
-
-
-PACKAGE BODY des_pkg IS
-
-
-  FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
-    VARIABLE result : std_logic_vector(0 TO 63);
-  BEGIN
-    FOR index IN 0 TO 63 LOOP
-      result( index ) := input_vector( ip_table( index ) );
-    END LOOP;
-    RETURN result;
-  END FUNCTION ip;
-
-  FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
-    VARIABLE result : std_logic_vector(0 TO 63);
-  BEGIN
-    FOR index IN 0 TO 63 LOOP
-      result( index ) := input_vector( ipn_table( index ) );
-    END LOOP;
-    RETURN result;
-  END FUNCTION ipn;
-
-  FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
-    VARIABLE result : std_logic_vector(0 TO 47);
-  BEGIN
-    FOR index IN 0 TO 47 LOOP
-      result( index ) := input_vector( e_table( index ) );
-    END LOOP;
-    RETURN result;
-  END FUNCTION e;
-
-  FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
-    VARIABLE int : std_logic_vector(0 TO 1);
-    VARIABLE i : integer RANGE 0 TO 3;
-    VARIABLE j : integer RANGE 0 TO 15;
-    VARIABLE result : std_logic_vector(0 TO 3);
-  BEGIN
-    int := input_vector( 0 ) & input_vector( 5 );
-    i := to_integer( unsigned( int ) );
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
-    result := std_logic_vector( to_unsigned( s1_table( i, j ), 4 ) );
-    RETURN result;
-  END FUNCTION s1;
-
-  FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
-    VARIABLE int : std_logic_vector(0 TO 1);
-    VARIABLE i : integer RANGE 0 TO 3;
-    VARIABLE j : integer RANGE 0 TO 15;
-    VARIABLE result : std_logic_vector(0 TO 3);
-  BEGIN
-    int := input_vector( 0 ) & input_vector( 5 );
-    i := to_integer( unsigned( int ) );
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
-    result := std_logic_vector( to_unsigned( s2_table( i, j ), 4 ) );
-    RETURN result;
-  END FUNCTION s2;
-
-  FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
-    VARIABLE int : std_logic_vector(0 TO 1);
-    VARIABLE i : integer RANGE 0 TO 3;
-    VARIABLE j : integer RANGE 0 TO 15;
-    VARIABLE result : std_logic_vector(0 TO 3);
-  BEGIN
-    int := input_vector( 0 ) & input_vector( 5 );
-    i := to_integer( unsigned( int ) );
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
-    result := std_logic_vector( to_unsigned( s3_table( i, j ), 4 ) );
-    RETURN result;
-  END FUNCTION s3;
-
-  FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
-    VARIABLE int : std_logic_vector(0 TO 1);
-    VARIABLE i : integer RANGE 0 TO 3;
-    VARIABLE j : integer RANGE 0 TO 15;
-    VARIABLE result : std_logic_vector(0 TO 3);
-  BEGIN
-    int := input_vector( 0 ) & input_vector( 5 );
-    i := to_integer( unsigned( int ) );
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
-    result := std_logic_vector( to_unsigned( s4_table( i, j ), 4 ) );
-    RETURN result;
-  END FUNCTION s4;
-
-  FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
-    VARIABLE int : std_logic_vector(0 TO 1);
-    VARIABLE i : integer RANGE 0 TO 3;
-    VARIABLE j : integer RANGE 0 TO 15;
-    VARIABLE result : std_logic_vector(0 TO 3);
-  BEGIN
-    int := input_vector( 0 ) & input_vector( 5 );
-    i := to_integer( unsigned( int ) );
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
-    result := std_logic_vector( to_unsigned( s5_table( i, j ), 4 ) );
-    RETURN result;
-  END FUNCTION s5;
-
-  FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
-    VARIABLE int : std_logic_vector(0 TO 1);
-    VARIABLE i : integer RANGE 0 TO 3;
-    VARIABLE j : integer RANGE 0 TO 15;
-    VARIABLE result : std_logic_vector(0 TO 3);
-  BEGIN
-    int := input_vector( 0 ) & input_vector( 5 );
-    i := to_integer( unsigned( int ) );
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
-    result := std_logic_vector( to_unsigned( s6_table( i, j ), 4 ) );
-    RETURN result;
-  END FUNCTION s6;
-
-  FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
-    VARIABLE int : std_logic_vector(0 TO 1);
-    VARIABLE i : integer RANGE 0 TO 3;
-    VARIABLE j : integer RANGE 0 TO 15;
-    VARIABLE result : std_logic_vector(0 TO 3);
-  BEGIN
-    int := input_vector( 0 ) & input_vector( 5 );
-    i := to_integer( unsigned( int ) );
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
-    result := std_logic_vector( to_unsigned( s7_table( i, j ), 4 ) );
-    RETURN result;
-  END FUNCTION s7;
-
-  FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
-    VARIABLE int : std_logic_vector(0 TO 1);
-    VARIABLE i : integer RANGE 0 TO 3;
-    VARIABLE j : integer RANGE 0 TO 15;
-    VARIABLE result : std_logic_vector(0 TO 3);
-  BEGIN
-    int := input_vector( 0 ) & input_vector( 5 );
-    i := to_integer( unsigned( int ) );
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
-    result := std_logic_vector( to_unsigned( s8_table( i, j ), 4 ) );
-    RETURN result;
-  END FUNCTION s8;
-
-  FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
-    VARIABLE result : std_logic_vector(0 TO 31);
-  BEGIN
-    FOR index IN 0 TO 31 LOOP
-      result( index ) := input_vector( p_table( index ) );
-    END LOOP;
-    RETURN result;
-  END FUNCTION p;
-
-  FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS
-    VARIABLE intern : std_logic_vector(0 TO 47);
-    VARIABLE result : std_logic_vector(0 TO 31);
-  BEGIN
-    intern := e( input_r ) xor input_key;
-    result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) &
-              s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) );
-    RETURN result;
-  END FUNCTION f;
-
-  FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
-    VARIABLE result : std_logic_vector(0 TO 27);
-  BEGIN
-    FOR index IN 0 TO 27 LOOP
-      result( index ) := input_vector( pc1c_table( index ) );
-    END LOOP;
-    RETURN result;
-  END FUNCTION pc1_c;
-
-  FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
-
-    VARIABLE result : std_logic_vector(0 TO 27);
-  BEGIN
-    FOR index IN 0 TO 27 LOOP
-      result( index ) := input_vector( pc1d_table( index ) );
-    END LOOP;
-    RETURN result;
-  END FUNCTION pc1_d;
-
-  FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS
-    VARIABLE result : std_logic_vector(0 TO 47);
-  BEGIN
-    FOR index IN 0 TO 47 LOOP
-      result( index ) := input_vector( pc2_table( index ) );
-    END LOOP;
-    RETURN result;
-  END FUNCTION pc2;
-
-
-END PACKAGE BODY des_pkg;
diff --git a/cbcdes/sim/vhdl/makefile b/cbcdes/sim/vhdl/Makefile
similarity index 60%
rename from cbcdes/sim/vhdl/makefile
rename to cbcdes/sim/vhdl/Makefile
index 00e8ee7..a91af0c 100644
--- a/cbcdes/sim/vhdl/makefile
+++ b/cbcdes/sim/vhdl/Makefile
@@ -19,22 +19,31 @@
 # ======================================================================
 
 
-SRC_FILES = ../../rtl/vhdl/des_pkg.vhd ../../rtl/vhdl/des.vhd ../../rtl/vhdl/cbcdes.vhd
+DESIGN_NAME := cbcdes
+SRC_FILES   := ../../../des/rtl/vhdl/des_pkg.vhd \
+               ../../../des/rtl/vhdl/des.vhd \
+               ../../rtl/vhdl/$(DESIGN_NAME).vhd
+VHD_STD     := 08
 
 
-all : sim wave
+.PHONY: sim
+sim : tb_$(DESIGN_NAME).ghw
+
+.PHONY: all
+all : wave
+
+
+tb_$(DESIGN_NAME).o: $(SRC_FILES) tb_$(DESIGN_NAME).vhd
+	ghdl -a --std=$(VHD_STD) $(SRC_FILES) tb_$(DESIGN_NAME).vhd
+
+tb_$(DESIGN_NAME).ghw : tb_$(DESIGN_NAME).o
+	ghdl -e --std=$(VHD_STD) tb_$(DESIGN_NAME)
+	ghdl -r tb_$(DESIGN_NAME) --wave=tb_$(DESIGN_NAME).ghw --assert-level=error
+
+wave : tb_$(DESIGN_NAME).ghw
+	gtkwave -S tb_$(DESIGN_NAME).tcl tb_$(DESIGN_NAME).ghw
 
-sim : tb_cbcdes.ghw
 
-tb_cbcdes.ghw : $(SRC_FILES) tb_cbcdes.vhd
-	ghdl -a $(SRC_FILES) tb_cbcdes.vhd
-	ghdl -e tb_cbcdes
-	ghdl -r tb_cbcdes --wave=tb_cbcdes.ghw --assert-level=error --stop-time=220us
-	
-wave : tb_cbcdes.ghw
-	gtkwave -T tb_cbcdes.tcl tb_cbcdes.ghw
-	
 clean :
-	echo "# cleaning simulation files"
-	rm -f *.ghw
-	rm -f work*.cf
+	echo "# Cleaning files"
+	rm -f *.ghw *.o tb_$(DESIGN_NAME) work*.cf
diff --git a/cbcdes/sim/vhdl/tb_cbcdes.tcl b/cbcdes/sim/vhdl/tb_cbcdes.tcl
index 681f0bd..b52daa7 100644
--- a/cbcdes/sim/vhdl/tb_cbcdes.tcl
+++ b/cbcdes/sim/vhdl/tb_cbcdes.tcl
@@ -2,12 +2,13 @@ set signals [list]
 lappend signals "top.tb_cbcdes.s_reset"
 lappend signals "top.tb_cbcdes.s_clk"
 lappend signals "top.tb_cbcdes.s_validin"
+lappend signals "top.tb_cbcdes.s_acceptin"
 lappend signals "top.tb_cbcdes.s_start"
 lappend signals "top.tb_cbcdes.s_mode"
 lappend signals "top.tb_cbcdes.s_key"
 lappend signals "top.tb_cbcdes.s_iv"
 lappend signals "top.tb_cbcdes.s_datain"
 lappend signals "top.tb_cbcdes.s_validout"
+lappend signals "top.tb_cbcdes.s_acceptout"
 lappend signals "top.tb_cbcdes.s_dataout"
-lappend signals "top.tb_cbcdes.s_ready"
 set num_added [ gtkwave::addSignalsFromList $signals ]
diff --git a/cbcdes/sim/vhdl/tb_cbcdes.vhd b/cbcdes/sim/vhdl/tb_cbcdes.vhd
index 352d0d1..4c6fccf 100644
--- a/cbcdes/sim/vhdl/tb_cbcdes.vhd
+++ b/cbcdes/sim/vhdl/tb_cbcdes.vhd
@@ -31,6 +31,9 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+use std.env.all;
+
+
 
 entity tb_cbcdes is
 end entity tb_cbcdes;
@@ -148,26 +151,10 @@ architecture rtl of tb_cbcdes is
   signal s_iv       : std_logic_vector(0 to 63) := (others => '0');
   signal s_datain   : std_logic_vector(0 to 63) := (others => '0');
   signal s_validin  : std_logic := '0';
-  signal s_ready    : std_logic := '0';
+  signal s_acceptin : std_logic;
   signal s_dataout  : std_logic_vector(0 to 63);
   signal s_validout : std_logic;
-
-
-  component cbcdes is
-    port (
-      reset_i     : in  std_logic;
-      clk_i       : in  std_logic;
-      mode_i      : in  std_logic;
-      start_i     : in  std_logic;
-      iv_i        : in  std_logic_vector(0 to 63);
-      key_i       : in  std_logic_vector(0 TO 63);
-      data_i      : in  std_logic_vector(0 TO 63);
-      valid_i     : in  std_logic;
-      ready_o     : out std_logic;
-      data_o      : out std_logic_vector(0 TO 63);
-      valid_o     : out std_logic
-    );
-  end component cbcdes;
+  signal s_acceptout : std_logic := '0';
 
 
 begin
@@ -188,13 +175,13 @@ begin
     s_datain  <= x"8000000000000000";
     -- Variable plaintext known answer test
     for index in c_variable_plaintext_known_answers'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         s_validin <= '1';
         s_start   <= '1';
         if(index /= 0) then
           s_datain <= '0' & s_datain(0 to 62);
         end if;
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
     end loop;
@@ -209,11 +196,11 @@ begin
     -- Inverse permutation known answer test
     s_key     <= x"0101010101010101";
     for index in c_variable_plaintext_known_answers'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         s_validin <= '1';
         s_start   <= '1';
         s_datain  <= c_variable_plaintext_known_answers(index);
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
     end loop;
@@ -228,7 +215,7 @@ begin
     -- Variable key known answer test
     s_key     <= x"8000000000000000";
     for index in c_variable_key_known_answers'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         s_validin <= '1';
         s_start   <= '1';
         if(index /= 0) then
@@ -239,7 +226,7 @@ begin
             s_key <= '0' & s_key(0 to 62);
           end if;
         end if;
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
     end loop;
@@ -254,11 +241,11 @@ begin
     -- Permutation operation known answer test
     s_datain <= x"0000000000000000";
     for index in c_permutation_operation_known_answers_keys'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         s_validin <= '1';
         s_start   <= '1';
         s_key     <= c_permutation_operation_known_answers_keys(index);
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
     end loop;
@@ -272,12 +259,12 @@ begin
     wait for 1 us;
     -- Substitution table known answer test
     for index in c_substitution_table_test_keys'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         s_validin <= '1';
         s_start   <= '1';
         s_key     <= c_substitution_table_test_keys(index);
         s_datain  <= c_substitution_table_test_plain(index);
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
     end loop;
@@ -291,7 +278,7 @@ begin
     wait for 1 us;
     -- cbc known answers test
     for index in c_substitution_table_test_keys'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         if(index = 0) then
           s_start <= '1';
           s_key   <= x"5555555555555555";
@@ -299,7 +286,7 @@ begin
         end if;
         s_validin <= '1';
         s_datain  <= c_substitution_table_test_plain(index);
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
     end loop;
@@ -315,12 +302,12 @@ begin
     -- Variable ciphertext known answer test
     s_key     <= x"0101010101010101";
     for index in c_variable_plaintext_known_answers'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         s_mode    <= '1';
         s_start   <= '1';
         s_validin <= '1';
         s_datain  <= c_variable_plaintext_known_answers(index);
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
         s_mode    <= '0';
@@ -337,14 +324,14 @@ begin
     s_key     <= x"0101010101010101";
     s_datain  <= x"8000000000000000";
     for index in c_variable_plaintext_known_answers'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         s_mode    <= '1';
         s_start   <= '1';
         s_validin <= '1';
         if(index /= 0) then
           s_datain <= '0' & s_datain(0 to 62);
         end if;
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
         s_mode    <= '0';
@@ -360,7 +347,7 @@ begin
     -- Variable key known answer test
     s_key     <= x"8000000000000000";
     for index in c_variable_key_known_answers'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         s_mode    <= '1';
         s_start   <= '1';
         s_validin <= '1';
@@ -373,7 +360,7 @@ begin
             s_key <= '0' & s_key(0 to 62);
           end if;
         end if;
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
         s_mode    <= '0';
@@ -388,13 +375,13 @@ begin
     wait for 1 us;
     -- Permutation operation known answer test
     for index in c_permutation_operation_known_answers_keys'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         s_mode    <= '1';
         s_start   <= '1';
         s_validin <= '1';
         s_datain  <= c_permutation_operation_known_answers_cipher(index);
         s_key     <= c_permutation_operation_known_answers_keys(index);
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
         s_mode    <= '0';
@@ -409,13 +396,13 @@ begin
     wait for 1 us;
     -- Substitution table known answer test
     for index in c_substitution_table_test_keys'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         s_mode    <= '1';
         s_start   <= '1';
         s_validin <= '1';
         s_key     <= c_substitution_table_test_keys(index);
         s_datain  <= c_substitution_table_test_cipher(index);
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
         s_mode    <= '0';
@@ -430,7 +417,7 @@ begin
     wait for 1 us;
     -- cbc known answer test
     for index in c_substitution_table_test_keys'range loop
-      wait until rising_edge(s_clk) and s_ready = '1';
+      wait until rising_edge(s_clk);
         if(index = 0) then
           s_mode  <= '1';
           s_start <= '1';
@@ -439,7 +426,7 @@ begin
         end if;
         s_validin <= '1';
         s_datain  <= s_cbc_answers(index);
-      wait until rising_edge(s_clk);
+      wait until rising_edge(s_clk) and s_acceptin = '1';
         s_validin <= '0';
         s_start   <= '0';
         s_mode    <= '0';
@@ -458,6 +445,7 @@ begin
   testcheckerP : process is
     variable v_plaintext : std_logic_vector(0 to 63) := x"8000000000000000";
   begin
+    s_acceptout <= '1';
     report "# ENCRYPTION TESTS";
     report "# Variable plaintext known answer test";
     for index in c_variable_plaintext_known_answers'range loop
@@ -545,11 +533,12 @@ begin
           severity error;
     end loop;
     report "# Successfully passed all tests";
-    wait;
+    wait for 10 us;
+    stop(0);
   end process testcheckerP;
 
 
-  i_cbcdes : cbcdes
+  i_cbcdes : entity work.cbcdes
   port map (
     reset_i  => s_reset,
     clk_i    => s_clk,
@@ -559,9 +548,10 @@ begin
     iv_i     => s_iv,
     data_i   => s_datain,
     valid_i  => s_validin, 
-    ready_o  => s_ready,              
+    accept_o => s_acceptin,              
     data_o   => s_dataout,
-    valid_o  => s_validout
+    valid_o  => s_validout,
+    accept_i => s_acceptout
   );
 
 
diff --git a/cbcdes/syn/vhdl/Makefile b/cbcdes/syn/vhdl/Makefile
new file mode 100644
index 0000000..ad3c2cb
--- /dev/null
+++ b/cbcdes/syn/vhdl/Makefile
@@ -0,0 +1,48 @@
+# ======================================================================
+# AES encryption/decryption
+# algorithm according to FIPS 197 specification
+# Copyright (C) 2020 Torsten Meissner
+#-----------------------------------------------------------------------
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+# ======================================================================
+
+
+DESIGN_NAME := cbcdes
+SRC_FILES   := ../../../des/rtl/vhdl/des_pkg.vhd \
+               ../../../des/rtl/vhdl/des.vhd \
+               ../../rtl/vhdl/$(DESIGN_NAME).vhd
+VHD_STD     := 08
+
+
+.PHONY: all
+all : $(DESIGN_NAME)_synth.vhd syn
+
+.PHONY: syn
+syn: $(DESIGN_NAME).json
+
+
+$(DESIGN_NAME).o: $(SRC_FILES)
+	ghdl -a --std=$(VHD_STD) $(SRC_FILES)
+
+$(DESIGN_NAME)_synth.vhd: $(SRC_FILES)
+	ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@
+
+$(DESIGN_NAME).json: $(DESIGN_NAME).o
+	yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@'
+
+
+clean :
+	echo "# Cleaning files"
+	rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd