From 5c4b112411779984a090d9c46fae590b1132f23d Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Fri, 23 Sep 2011 00:42:31 +0200 Subject: [PATCH] Initial Release of CBC-DES cbcdes.vhd and tb_cbcdes.vhd are still incomplete, maybe they contain some bugs --- cbcdes/rtl/cbcdes.vhd | 138 ++++++++++++ cbcdes/rtl/des.vhd | 336 +++++++++++++++++++++++++++++ cbcdes/rtl/des_pkg.vhd | 333 +++++++++++++++++++++++++++++ cbcdes/sim/makefile | 41 ++++ cbcdes/sim/tb_cbcdes.vhd | 446 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 1294 insertions(+) create mode 100644 cbcdes/rtl/cbcdes.vhd create mode 100644 cbcdes/rtl/des.vhd create mode 100644 cbcdes/rtl/des_pkg.vhd create mode 100644 cbcdes/sim/makefile create mode 100644 cbcdes/sim/tb_cbcdes.vhd diff --git a/cbcdes/rtl/cbcdes.vhd b/cbcdes/rtl/cbcdes.vhd new file mode 100644 index 0000000..c5a9a5a --- /dev/null +++ b/cbcdes/rtl/cbcdes.vhd @@ -0,0 +1,138 @@ +-- ====================================================================== +-- CBC-DES encryption/decryption +-- algorithm according to FIPS 46-3 specification +-- Copyright (C) 2007 Torsten Meissner +------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- ====================================================================== + + +-- Revision 0.1 2011/09/23 +-- Initial release, incomplete and may contain bugs + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.des_pkg.all; + + +entity cbcdes is + port ( + reset_i : in std_logic; -- low active async reset + clk_i : in std_logic; -- clock + start_i : in std_logic; -- start cbc + mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt + key_i : in std_logic_vector(0 TO 63); -- key input + iv_i : in std_logic_vector(0 to 63); -- iv input + data_i : in std_logic_vector(0 TO 63); -- data input + valid_i : in std_logic; -- input key/data valid flag + ready_o : out std_logic; -- ready to encrypt/decrypt + data_o : out std_logic_vector(0 TO 63); -- data output + valid_o : out std_logic -- output data valid flag + ); +end entity cbcdes; + + +architecture rtl of cbcdes is + + + component des is + port ( + clk_i : IN std_logic; -- clock + mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt + key_i : IN std_logic_vector(0 TO 63); -- key input + data_i : IN std_logic_vector(0 TO 63); -- data input + valid_i : IN std_logic; -- input key/data valid flag + data_o : OUT std_logic_vector(0 TO 63); -- data output + valid_o : OUT std_logic -- output data valid flag + ); + end component des; + + + signal s_mode : std_logic; + signal s_start : std_logic; + signal s_iv : std_logic_vector(0 to 63); + signal s_datain : std_logic_vector(0 to 63); + signal s_des_datain : std_logic_vector(0 to 63); + signal s_validin : std_logic; + signal s_dataout : std_logic_vector(0 to 63); + signal s_validout : std_logic; + signal s_ready : std_logic; + signal s_reset : std_logic; + + +begin + + + s_des_datain <= iv_i xor data_i when mode_i = '0' and start_i = '1' else + s_dataout xor data_i when mode_i = '0' and start_i = '0' else + data_i; + data_o <= s_iv xor s_dataout when s_mode = '1' and s_start = '1' else + s_datain xor s_dataout when s_mode = '1' and s_start = '0' else + s_dataout; + + ready_o <= s_ready; + s_validin <= valid_i and s_ready; + valid_o <= s_validout; + + inputregister : process(clk_i, reset_i) is + begin + if(reset_i = '0') then + s_reset <= '0'; + s_mode <= '0'; + s_start <= '0'; + s_iv <= (others => '0'); + s_datain <= (others => '0'); + elsif(rising_edge(clk_i)) then + s_reset <= reset_i; + if(valid_i = '1' and s_ready = '1') then + s_mode <= mode_i; + s_start <= start_i; + s_iv <= iv_i; + s_datain <= data_i; + end if; + end if; + end process inputregister; + + + outputregister : process(clk_i, reset_i) is + begin + if(reset_i = '0') then + s_ready <= '0'; + elsif(rising_edge(clk_i)) then + if(valid_i = '1' and s_ready = '1') then + s_ready <= '0'; + end if; + if(s_validout = '1' or (reset_i = '1' and s_reset = '0')) then + s_ready <= '1'; + end if; + end if; + end process outputregister; + + + i_des : des + port map ( + clk_i => clk_i, + mode_i => mode_i, + key_i => key_i, + data_i => s_des_datain, + valid_i => s_validin, + data_o => s_dataout, + valid_o => s_validout + ); + + +end architecture rtl; diff --git a/cbcdes/rtl/des.vhd b/cbcdes/rtl/des.vhd new file mode 100644 index 0000000..ad7bbdd --- /dev/null +++ b/cbcdes/rtl/des.vhd @@ -0,0 +1,336 @@ +-- ====================================================================== +-- DES encryption/decryption +-- algorithm according to FIPS 46-3 specification +-- Copyright (C) 2007 Torsten Meissner +------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- ====================================================================== + + +-- Revision 1.0 2007/02/04 +-- Initial release +-- Revision 1.1 2007/02/05 +-- Corrected error in use of mode register for key calculation + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.ALL; +USE work.des_pkg.ALL; + + +ENTITY des IS + PORT ( + clk_i : IN std_logic; -- clock + mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt + key_i : IN std_logic_vector(0 TO 63); -- key input + data_i : IN std_logic_vector(0 TO 63); -- data input + valid_i : IN std_logic; -- input key/data valid flag + data_o : OUT std_logic_vector(0 TO 63); -- data output + valid_o : OUT std_logic -- output data valid flag + ); +END ENTITY des; + + +ARCHITECTURE rtl OF des IS + +BEGIN + + crypt : PROCESS ( clk_i ) IS + -- variables for key calculation + VARIABLE c0 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c1 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c2 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c3 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c4 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c5 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c6 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c7 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c8 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c9 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d0 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d1 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d2 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d3 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d4 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d5 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d6 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d7 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d8 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d9 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0'); + -- key variables + VARIABLE key1 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key2 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key3 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key4 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key5 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key6 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key7 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key8 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key9 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0'); + -- variables for left & right data blocks + VARIABLE l0 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l1 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l2 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l3 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l4 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l5 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l6 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l7 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l8 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l9 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r0 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r1 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r2 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r3 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r4 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r5 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r6 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r7 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r8 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r9 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0'); + -- variables for mode & valid shift registers + VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0'); + VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0'); + BEGIN + IF rising_edge( clk_i ) THEN + -- shift registers + valid(1 TO 17) := valid(0 TO 16); + valid(0) := valid_i; + mode(1 TO 16) := mode(0 TO 15); + mode(0) := mode_i; + -- output stage + valid_o <= valid(17); + data_o <= ipn( ( r16 & l16 ) ); + -- 16. stage + IF mode(16) = '0' THEN + c16 := c15(1 TO 27) & c15(0); + d16 := d15(1 TO 27) & d15(0); + ELSE + c16 := c15(27) & c15(0 TO 26); + d16 := d15(27) & d15(0 TO 26); + END IF; + key16 := pc2( ( c16 & d16 ) ); + l16 := r15; + r16 := l15 xor ( f( r15, key16 ) ); + -- 15. stage + IF mode(15) = '0' THEN + c15 := c14(2 TO 27) & c14(0 TO 1); + d15 := d14(2 TO 27) & d14(0 TO 1); + ELSE + c15 := c14(26 TO 27) & c14(0 TO 25); + d15 := d14(26 TO 27) & d14(0 TO 25); + END IF; + key15 := pc2( ( c15 & d15 ) ); + l15 := r14; + r15 := l14 xor ( f( r14, key15 ) ); + -- 14. stage + IF mode(14) = '0' THEN + c14 := c13(2 TO 27) & c13(0 TO 1); + d14 := d13(2 TO 27) & d13(0 TO 1); + ELSE + c14 := c13(26 TO 27) & c13(0 TO 25); + d14 := d13(26 TO 27) & d13(0 TO 25); + END IF; + key14 := pc2( ( c14 & d14 ) ); + l14 := r13; + r14 := l13 xor ( f( r13, key14 ) ); + -- 13. stage + IF mode(13) = '0' THEN + c13 := c12(2 TO 27) & c12(0 TO 1); + d13 := d12(2 TO 27) & d12(0 TO 1); + ELSE + c13 := c12(26 TO 27) & c12(0 TO 25); + d13 := d12(26 TO 27) & d12(0 TO 25); + END IF; + key13 := pc2( ( c13 & d13 ) ); + l13 := r12; + r13 := l12 xor ( f( r12, key13 ) ); + -- 12. stage + IF mode(12) = '0' THEN + c12 := c11(2 TO 27) & c11(0 TO 1); + d12 := d11(2 TO 27) & d11(0 TO 1); + ELSE + c12 := c11(26 TO 27) & c11(0 TO 25); + d12 := d11(26 TO 27) & d11(0 TO 25); + END IF; + key12 := pc2( ( c12 & d12 ) ); + l12 := r11; + r12 := l11 xor ( f( r11, key12 ) ); + -- 11. stage + IF mode(11) = '0' THEN + c11 := c10(2 TO 27) & c10(0 TO 1); + d11 := d10(2 TO 27) & d10(0 TO 1); + ELSE + c11 := c10(26 TO 27) & c10(0 TO 25); + d11 := d10(26 TO 27) & d10(0 TO 25); + END IF; + key11 := pc2( ( c11 & d11 ) ); + l11 := r10; + r11 := l10 xor ( f( r10, key11 ) ); + -- 10. stage + IF mode(10) = '0' THEN + c10 := c9(2 TO 27) & c9(0 TO 1); + d10 := d9(2 TO 27) & d9(0 TO 1); + ELSE + c10 := c9(26 TO 27) & c9(0 TO 25); + d10 := d9(26 TO 27) & d9(0 TO 25); + END IF; + key10 := pc2( ( c10 & d10 ) ); + l10 := r9; + r10 := l9 xor ( f( r9, key10 ) ); + -- 9. stage + IF mode(9) = '0' THEN + c9 := c8(1 TO 27) & c8(0); + d9 := d8(1 TO 27) & d8(0); + ELSE + c9 := c8(27) & c8(0 TO 26); + d9 := d8(27) & d8(0 TO 26); + END IF; + key9 := pc2( ( c9 & d9 ) ); + l9 := r8; + r9 := l8 xor ( f( r8, key9 ) ); + -- 8. stage + IF mode(8) = '0' THEN + c8 := c7(2 TO 27) & c7(0 TO 1); + d8 := d7(2 TO 27) & d7(0 TO 1); + ELSE + c8 := c7(26 TO 27) & c7(0 TO 25); + d8 := d7(26 TO 27) & d7(0 TO 25); + END IF; + key8 := pc2( ( c8 & d8 ) ); + l8 := r7; + r8 := l7 xor ( f( r7, key8 ) ); + -- 7. stage + IF mode(7) = '0' THEN + c7 := c6(2 TO 27) & c6(0 TO 1); + d7 := d6(2 TO 27) & d6(0 TO 1); + ELSE + c7 := c6(26 TO 27) & c6(0 TO 25); + d7 := d6(26 TO 27) & d6(0 TO 25); + END IF; + key7 := pc2( ( c7 & d7 ) ); + l7 := r6; + r7 := l6 xor ( f( r6, key7 ) ); + -- 6. stage + IF mode(6) = '0' THEN + c6 := c5(2 TO 27) & c5(0 TO 1); + d6 := d5(2 TO 27) & d5(0 TO 1); + ELSE + c6 := c5(26 TO 27) & c5(0 TO 25); + d6 := d5(26 TO 27) & d5(0 TO 25); + END IF; + key6 := pc2( ( c6 & d6 ) ); + l6 := r5; + r6 := l5 xor ( f( r5, key6 ) ); + -- 5. stage + IF mode(5) = '0' THEN + c5 := c4(2 TO 27) & c4(0 TO 1); + d5 := d4(2 TO 27) & d4(0 TO 1); + ELSE + c5 := c4(26 TO 27) & c4(0 TO 25); + d5 := d4(26 TO 27) & d4(0 TO 25); + END IF; + key5 := pc2( ( c5 & d5 ) ); + l5 := r4; + r5 := l4 xor ( f( r4, key5 ) ); + -- 4. stage + IF mode(4) = '0' THEN + c4 := c3(2 TO 27) & c3(0 TO 1); + d4 := d3(2 TO 27) & d3(0 TO 1); + ELSE + c4 := c3(26 TO 27) & c3(0 TO 25); + d4 := d3(26 TO 27) & d3(0 TO 25); + END IF; + key4 := pc2( ( c4 & d4 ) ); + l4 := r3; + r4 := l3 xor ( f( r3, key4 ) ); + -- 3. stage + IF mode(3) = '0' THEN + c3 := c2(2 TO 27) & c2(0 TO 1); + d3 := d2(2 TO 27) & d2(0 TO 1); + ELSE + c3 := c2(26 TO 27) & c2(0 TO 25); + d3 := d2(26 TO 27) & d2(0 TO 25); + END IF; + key3 := pc2( ( c3 & d3 ) ); + l3 := r2; + r3 := l2 xor ( f( r2, key3 ) ); + -- 2. stage + IF mode(2) = '0' THEN + c2 := c1(1 TO 27) & c1(0); + d2 := d1(1 TO 27) & d1(0); + ELSE + c2 := c1(27) & c1(0 TO 26); + d2 := d1(27) & d1(0 TO 26); + END IF; + key2 := pc2( ( c2 & d2 ) ); + l2 := r1; + r2 := l1 xor ( f( r1, key2 ) ); + -- 1. stage + IF mode(1) = '0' THEN + c1 := c0(1 TO 27) & c0(0); + d1 := d0(1 TO 27) & d0(0); + ELSE + c1 := c0; + d1 := d0; + END IF; + key1 := pc2( ( c1 & d1 ) ); + l1 := r0; + r1 := l0 xor ( f( r0, key1 ) ); + -- input stage + l0 := ip( data_i )(0 TO 31); + r0 := ip( data_i )(32 TO 63); + c0 := pc1_c( key_i ); + d0 := pc1_d( key_i ); + END IF; + END PROCESS crypt; + +END ARCHITECTURE rtl; diff --git a/cbcdes/rtl/des_pkg.vhd b/cbcdes/rtl/des_pkg.vhd new file mode 100644 index 0000000..384209e --- /dev/null +++ b/cbcdes/rtl/des_pkg.vhd @@ -0,0 +1,333 @@ +-- ====================================================================== +-- DES encryption/decryption +-- package file with functions +-- Copyright (C) 2007 Torsten Meissner +------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- ====================================================================== + + +-- Revision 1.0 2007/02/04 +-- Initial release + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.ALL; + + +PACKAGE des_pkg IS + + FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; + FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; + + FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; + FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; + + FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; + + FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector; + + FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; + FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; + FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector; + +END PACKAGE des_pkg; + + +PACKAGE BODY des_pkg IS + + FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63; + VARIABLE table : matrix := (57, 49, 41, 33, 25, 17, 9, 1, + 59, 51, 43, 35, 27, 19, 11, 3, + 61, 53, 45, 37, 29, 21, 13, 5, + 63, 55, 47, 39, 31, 23, 15, 7, + 56, 48, 40, 32, 24, 16, 8, 0, + 58, 50, 42, 34, 26, 18, 10, 2, + 60, 52, 44, 36, 28, 20, 12, 4, + 62, 54, 46, 38, 30, 22, 14, 6); + VARIABLE result : std_logic_vector(0 TO 63); + BEGIN + FOR index IN 0 TO 63 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION ip; + + FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63; + VARIABLE table : matrix := (39, 7, 47, 15, 55, 23, 63, 31, + 38, 6, 46, 14, 54, 22, 62, 30, + 37, 5, 45, 13, 53, 21, 61, 29, + 36, 4, 44, 12, 52, 20, 60, 28, + 35, 3, 43, 11, 51, 19, 59, 27, + 34, 2, 42, 10, 50, 18, 58, 26, + 33, 1, 41, 9, 49, 17, 57, 25, + 32, 0, 40, 8, 48, 16, 56, 24); + VARIABLE result : std_logic_vector(0 TO 63); + BEGIN + FOR index IN 0 TO 63 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION ipn; + + FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31; + VARIABLE table : matrix := (31, 0, 1, 2, 3, 4, + 3, 4, 5, 6, 7, 8, + 7, 8, 9, 10, 11, 12, + 11, 12, 13, 14, 15, 16, + 15, 16, 17, 18, 19, 20, + 19, 20, 21, 22, 23, 24, + 23, 24, 25, 26, 27, 28, + 27, 28, 29, 30, 31, 0); + VARIABLE result : std_logic_vector(0 TO 47); + BEGIN + FOR index IN 0 TO 47 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION e; + + FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => (14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7), + 1 => ( 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8), + 2 => ( 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0), + 3 => (15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s1; + + FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => (15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10), + 1 => ( 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5), + 2 => ( 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15), + 3 => (13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s2; + + FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => (10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8), + 1 => (13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1), + 2 => (13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7), + 3 => ( 1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s3; + + FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => ( 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15), + 1 => (13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9), + 2 => (10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4), + 3 => ( 3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s4; + + FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => ( 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9), + 1 => (14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6), + 2 => ( 4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14), + 3 => (11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s5; + + FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => (12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11), + 1 => (10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8), + 2 => ( 9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6), + 3 => ( 4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s6; + + FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => ( 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1), + 1 => (13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6), + 2 => ( 1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2), + 3 => ( 6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s7; + + FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + VARIABLE table : matrix := (0 => (13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7), + 1 => ( 1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2), + 2 => ( 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8), + 3 => ( 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11)); + VARIABLE int : std_logic_vector(0 TO 1); + VARIABLE i : integer RANGE 0 TO 3; + VARIABLE j : integer RANGE 0 TO 15; + VARIABLE result : std_logic_vector(0 TO 3); + BEGIN + int := input_vector( 0 ) & input_vector( 5 ); + i := to_integer( unsigned( int ) ); + j := to_integer( unsigned( input_vector( 1 TO 4) ) ); + result := std_logic_vector( to_unsigned( table( i, j ), 4 ) ); + RETURN result; + END FUNCTION s8; + + FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31; + VARIABLE table : matrix := (15, 6, 19, 20, + 28, 11, 27, 16, + 0, 14, 22, 25, + 4, 17, 30, 9, + 1, 7, 23, 13, + 31, 26, 2, 8, + 18, 12, 29, 5, + 21, 10, 3, 24); + VARIABLE result : std_logic_vector(0 TO 31); + BEGIN + FOR index IN 0 TO 31 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION p; + + FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS + VARIABLE intern : std_logic_vector(0 TO 47); + VARIABLE result : std_logic_vector(0 TO 31); + BEGIN + intern := e( input_r ) xor input_key; + result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) & + s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) ); + RETURN result; + END FUNCTION f; + + FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63; + VARIABLE table : matrix := (56, 48, 40, 32, 24, 16, 8, + 0, 57, 49, 41, 33, 25, 17, + 9, 1, 58, 50, 42, 34, 26, + 18, 10, 2, 59, 51, 43, 35); + VARIABLE result : std_logic_vector(0 TO 27); + BEGIN + FOR index IN 0 TO 27 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION pc1_c; + + FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63; + VARIABLE table : matrix := (62, 54, 46, 38, 30, 22, 14, + 6, 61, 53, 45, 37, 29, 21, + 13, 5, 60, 52, 44, 36, 28, + 20, 12, 4, 27, 19, 11, 3); + VARIABLE result : std_logic_vector(0 TO 27); + BEGIN + FOR index IN 0 TO 27 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION pc1_d; + + FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS + TYPE matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63; + VARIABLE table : matrix := (13, 16, 10, 23, 0, 4, + 2, 27, 14, 5, 20, 9, + 22, 18, 11, 3, 25, 7, + 15, 6, 26, 19, 12, 1, + 40, 51, 30, 36, 46, 54, + 29, 39, 50, 44, 32, 47, + 43, 48, 38, 55, 33, 52, + 45, 41, 49, 35, 28, 31); + VARIABLE result : std_logic_vector(0 TO 47); + BEGIN + FOR index IN 0 TO 47 LOOP + result( index ) := input_vector( table( index ) ); + END LOOP; + RETURN result; + END FUNCTION pc2; + + +END PACKAGE BODY des_pkg; \ No newline at end of file diff --git a/cbcdes/sim/makefile b/cbcdes/sim/makefile new file mode 100644 index 0000000..6b2c0e3 --- /dev/null +++ b/cbcdes/sim/makefile @@ -0,0 +1,41 @@ +# ====================================================================== +# DES encryption/decryption +# algorithm according to FIPS 46-3 specification +# Copyright (C) 2011 Torsten Meissner +#----------------------------------------------------------------------- +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# ====================================================================== + + +# Revision 1.0 2011/09/23 +# Initial release + + +all : sim wave + +sim : tb_cbcdes.ghw + +tb_cbcdes.ghw : ../rtl/*.vhd tb_cbcdes.vhd + ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/cbcdes.vhd tb_cbcdes.vhd + ghdl -e tb_cbcdes + ghdl -r tb_cbcdes --wave=tb_cbcdes.ghw --assert-level=error --stop-time=30us + +wave : tb_cbcdes.ghw + gtkwave tb_cbcdes.ghw + +clean : + echo "# cleaning simulation files" + rm -f *.ghw + rm -f work*.cf diff --git a/cbcdes/sim/tb_cbcdes.vhd b/cbcdes/sim/tb_cbcdes.vhd new file mode 100644 index 0000000..9225a5d --- /dev/null +++ b/cbcdes/sim/tb_cbcdes.vhd @@ -0,0 +1,446 @@ +-- ====================================================================== +-- CBC-DES encryption/decryption testbench +-- tests according to NIST 800-17 special publication +-- Copyright (C) 2011 Torsten Meissner +------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- ====================================================================== + + +-- Revision 1.0 2011/09/23 +-- Initial release, variable plaintext known answer test integrated + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity tb_cbcdes is +end entity tb_cbcdes; + + +architecture rtl of tb_cbcdes is + + + type t_array is array (natural range <>) of std_logic_vector(0 to 63); + + constant c_variable_plaintext_known_answers : t_array(0 to 63) := + (x"95F8A5E5DD31D900", x"DD7F121CA5015619", x"2E8653104F3834EA", + x"4BD388FF6CD81D4F", x"20B9E767B2FB1456", x"55579380D77138EF", + x"6CC5DEFAAF04512F", x"0D9F279BA5D87260", x"D9031B0271BD5A0A", + x"424250B37C3DD951", x"B8061B7ECD9A21E5", x"F15D0F286B65BD28", + x"ADD0CC8D6E5DEBA1", x"E6D5F82752AD63D1", x"ECBFE3BD3F591A5E", + x"F356834379D165CD", x"2B9F982F20037FA9", x"889DE068A16F0BE6", + x"E19E275D846A1298", x"329A8ED523D71AEC", x"E7FCE22557D23C97", + x"12A9F5817FF2D65D", x"A484C3AD38DC9C19", x"FBE00A8A1EF8AD72", + x"750D079407521363", x"64FEED9C724C2FAF", x"F02B263B328E2B60", + x"9D64555A9A10B852", x"D106FF0BED5255D7", x"E1652C6B138C64A5", + x"E428581186EC8F46", x"AEB5F5EDE22D1A36", x"E943D7568AEC0C5C", + x"DF98C8276F54B04B", x"B160E4680F6C696F", x"FA0752B07D9C4AB8", + x"CA3A2B036DBC8502", x"5E0905517BB59BCF", x"814EEB3B91D90726", + x"4D49DB1532919C9F", x"25EB5FC3F8CF0621", x"AB6A20C0620D1C6F", + x"79E90DBC98F92CCA", x"866ECEDD8072BB0E", x"8B54536F2F3E64A8", + x"EA51D3975595B86B", x"CAFFC6AC4542DE31", x"8DD45A2DDF90796C", + x"1029D55E880EC2D0", x"5D86CB23639DBEA9", x"1D1CA853AE7C0C5F", + x"CE332329248F3228", x"8405D1ABE24FB942", x"E643D78090CA4207", + x"48221B9937748A23", x"DD7C0BBD61FAFD54", x"2FBC291A570DB5C4", + x"E07C30D7E4E26E12", x"0953E2258E8E90A1", x"5B711BC4CEEBF2EE", + x"CC083F1E6D9E85F6", x"D2FD8867D50D2DFE", x"06E7EA22CE92708F", + x"166B40B44ABA4BD6"); + + constant c_variable_key_known_answers : t_array(0 to 55) := + (x"95A8D72813DAA94D", x"0EEC1487DD8C26D5", x"7AD16FFB79C45926", + x"D3746294CA6A6CF3", x"809F5F873C1FD761", x"C02FAFFEC989D1FC", + x"4615AA1D33E72F10", x"2055123350C00858", x"DF3B99D6577397C8", + x"31FE17369B5288C9", x"DFDD3CC64DAE1642", x"178C83CE2B399D94", + x"50F636324A9B7F80", x"A8468EE3BC18F06D", x"A2DC9E92FD3CDE92", + x"CAC09F797D031287", x"90BA680B22AEB525", x"CE7A24F350E280B6", + x"882BFF0AA01A0B87", x"25610288924511C2", x"C71516C29C75D170", + x"5199C29A52C9F059", x"C22F0A294A71F29F", x"EE371483714C02EA", + x"A81FBD448F9E522F", x"4F644C92E192DFED", x"1AFA9A66A6DF92AE", + x"B3C1CC715CB879D8", x"19D032E64AB0BD8B", x"3CFAA7A7DC8720DC", + x"B7265F7F447AC6F3", x"9DB73B3C0D163F54", x"8181B65BABF4A975", + x"93C9B64042EAA240", x"5570530829705592", x"8638809E878787A0", + x"41B9A79AF79AC208", x"7A9BE42F2009A892", x"29038D56BA6D2745", + x"5495C6ABF1E5DF51", x"AE13DBD561488933", x"024D1FFA8904E389", + x"D1399712F99BF02E", x"14C1D7C1CFFEC79E", x"1DE5279DAE3BED6F", + x"E941A33F85501303", x"DA99DBBC9A03F379", x"B7FC92F91D8E92E9", + x"AE8E5CAA3CA04E85", x"9CC62DF43B6EED74", x"D863DBB5C59A91A0", + x"A1AB2190545B91D7", x"0875041E64C570F7", x"5A594528BEBEF1CC", + x"FCDB3291DE21F0C0", x"869EFD7F9F265A09"); + + constant c_permutation_operation_known_answers_keys : t_array(0 to 31) := + (x"1046913489980131", x"1007103489988020", x"10071034C8980120", + x"1046103489988020", x"1086911519190101", x"1086911519580101", + x"5107B01519580101", x"1007B01519190101", x"3107915498080101", + x"3107919498080101", x"10079115B9080140", x"3107911598080140", + x"1007D01589980101", x"9107911589980101", x"9107D01589190101", + x"1007D01598980120", x"1007940498190101", x"0107910491190401", + x"0107910491190101", x"0107940491190401", x"19079210981A0101", + x"1007911998190801", x"10079119981A0801", x"1007921098190101", + x"100791159819010B", x"1004801598190101", x"1004801598190102", + x"1004801598190108", x"1002911598100104", x"1002911598190104", + x"1002911598100201", x"1002911698100101"); + + constant c_permutation_operation_known_answers_cipher : t_array(0 to 31) := + (x"88D55E54F54C97B4", x"0C0CC00C83EA48FD", x"83BC8EF3A6570183", + x"DF725DCAD94EA2E9", x"E652B53B550BE8B0", x"AF527120C485CBB0", + x"0F04CE393DB926D5", x"C9F00FFC74079067", x"7CFD82A593252B4E", + x"CB49A2F9E91363E3", x"00B588BE70D23F56", x"406A9A6AB43399AE", + x"6CB773611DCA9ADA", x"67FD21C17DBB5D70", x"9592CB4110430787", + x"A6B7FF68A318DDD3", x"4D102196C914CA16", x"2DFA9F4573594965", + x"B46604816C0E0774", x"6E7E6221A4F34E87", x"AA85E74643233199", + x"2E5A19DB4D1962D6", x"23A866A809D30894", x"D812D961F017D320", + x"055605816E58608F", x"ABD88E8B1B7716F1", x"537AC95BE69DA1E1", + x"AED0F6AE3C25CDD8", x"B3E35A5EE53E7B8D", x"61C79C71921A2EF8", + x"E2F5728F0995013C", x"1AEAC39A61F0A464"); + + constant c_substitution_table_test_keys : t_array(0 to 18) := + (x"7CA110454A1A6E57", x"0131D9619DC1376E", x"07A1133E4A0B2686", + x"3849674C2602319E", x"04B915BA43FEB5B6", x"0113B970FD34F2CE", + x"0170F175468FB5E6", x"43297FAD38E373FE", x"07A7137045DA2A16", + x"04689104C2FD3B2F", x"37D06BB516CB7546", x"1F08260D1AC2465E", + x"584023641ABA6176", x"025816164629B007", x"49793EBC79B3258F", + x"4FB05E1515AB73A7", x"49E95D6D4CA229BF", x"018310DC409B26D6", + x"1C587F1C13924FEF"); + + constant c_substitution_table_test_plain : t_array(0 to 18) := + (x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172", + x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A", + x"0756D8E0774761D2", x"762514B829BF486A", x"3BDD119049372802", + x"26955F6835AF609A", x"164D5E404F275232", x"6B056E18759F5CCA", + x"004BD6EF09176062", x"480D39006EE762F2", x"437540C8698F3CFA", + x"072D43A077075292", x"02FE55778117F12A", x"1D9D5C5018F728C2", + x"305532286D6F295A"); + + constant c_substitution_table_test_cipher : t_array(0 to 18) := + (x"690F5B0D9A26939B", x"7A389D10354BD271", x"868EBB51CAB4599A", + x"7178876E01F19B2A", x"AF37FB421F8C4095", x"86A560F10EC6D85B", + x"0CD3DA020021DC09", x"EA676B2CB7DB2B7A", x"DFD64A815CAF1A0F", + x"5C513C9C4886C088", x"0A2AEEAE3FF4AB77", x"EF1BF03E5DFA575A", + x"88BF0DB6D70DEE56", x"A1F9915541020B56", x"6FBF1CAFCFFD0556", + x"2F22E49BAB7CA1AC", x"5A6B612CC26CCE4A", x"5F4C038ED12B2E41", + x"63FAC0D034D9F793"); + + signal s_reset : std_logic := '0'; + signal s_clk : std_logic := '0'; + signal s_start : std_logic := '0'; + signal s_mode : std_logic := '0'; + signal s_key : std_logic_vector(0 to 63) := (others => '0'); + signal s_iv : std_logic_vector(0 to 63) := (others => '0'); + signal s_datain : std_logic_vector(0 to 63) := (others => '0'); + signal s_validin : std_logic := '0'; + signal s_ready : std_logic := '0'; + signal s_dataout : std_logic_vector(0 to 63); + signal s_validout : std_logic; + + + component cbcdes is + port ( + reset_i : in std_logic; + clk_i : in std_logic; + mode_i : in std_logic; + start_i : in std_logic; + iv_i : in std_logic_vector(0 to 63); + key_i : in std_logic_vector(0 TO 63); + data_i : in std_logic_vector(0 TO 63); + valid_i : in std_logic; + ready_o : out std_logic; + data_o : out std_logic_vector(0 TO 63); + valid_o : out std_logic + ); + end component cbcdes; + + +begin + + + s_reset <= '1' after 100 ns; + s_clk <= not(s_clk) after 10 ns; + + + teststimuliP : process is + begin + -- ENCRYPTION TESTS + s_start <= '0'; + s_mode <= '0'; + s_validin <= '0'; + s_iv <= (others => '0'); + s_key <= x"0101010101010101"; + s_datain <= x"8000000000000000"; + -- Variable plaintext known answer test + for index in c_variable_plaintext_known_answers'range loop + wait until rising_edge(s_clk) and s_ready = '1'; + s_validin <= '1'; + s_start <= '1'; + if(index /= 0) then + s_datain <= '0' & s_datain(0 to 62); + end if; + wait until rising_edge(s_clk); + s_validin <= '0'; + s_start <= '0'; + end loop; + wait until rising_edge(s_clk); + s_start <= '0'; + s_mode <= '0'; + s_validin <= '0'; + s_iv <= (others => '0'); + s_key <= (others => '0'); + s_datain <= (others => '0'); +-- wait for 100 ns; +-- -- Inverse permutation known answer test +-- s_key <= x"0101010101010101"; +-- for index in c_variable_plaintext_known_answers'range loop +-- wait until rising_edge(s_clk); +-- s_validin <= '1'; +-- s_datain <= c_variable_plaintext_known_answers(index); +-- end loop; +-- wait until rising_edge(s_clk); +-- s_mode <= '0'; +-- s_validin <= '0'; +-- s_key <= (others => '0'); +-- s_datain <= (others => '0'); +-- wait for 100 ns; +-- -- Variable key known answer test +-- s_key <= x"8000000000000000"; +-- for index in c_variable_key_known_answers'range loop +-- wait until rising_edge(s_clk); +-- s_validin <= '1'; +-- if(index /= 0) then +-- if(index = 7 or index = 14 or index = 21 or index = 28 or index = 35 or +-- index = 42 or index = 49) then +-- s_key <= "00" & s_key(0 to 61); +-- else +-- s_key <= '0' & s_key(0 to 62); +-- end if; +-- end if; +-- end loop; +-- wait until rising_edge(s_clk); +-- s_mode <= '0'; +-- s_validin <= '0'; +-- s_key <= (others => '0'); +-- s_datain <= (others => '0'); +-- wait for 100 ns; +-- -- Permutation operation known answer test +-- s_datain <= x"0000000000000000"; +-- for index in c_permutation_operation_known_answers_keys'range loop +-- wait until rising_edge(s_clk); +-- s_validin <= '1'; +-- s_key <= c_permutation_operation_known_answers_keys(index); +-- end loop; +-- wait until rising_edge(s_clk); +-- s_mode <= '0'; +-- s_validin <= '0'; +-- s_key <= (others => '0'); +-- s_datain <= (others => '0'); +-- wait for 100 ns; +-- -- Substitution table known answer test +-- for index in c_substitution_table_test_keys'range loop +-- wait until rising_edge(s_clk); +-- s_validin <= '1'; +-- s_key <= c_substitution_table_test_keys(index); +-- s_datain <= c_substitution_table_test_plain(index); +-- end loop; +-- wait until rising_edge(s_clk); +-- -- DECRYPTION TESTS +-- s_mode <= '0'; +-- s_validin <= '0'; +-- s_key <= (others => '0'); +-- s_datain <= (others => '0'); +-- wait for 100 ns; +-- -- Variable ciphertext known answer test +-- s_key <= x"0101010101010101"; +-- for index in c_variable_plaintext_known_answers'range loop +-- wait until rising_edge(s_clk); +-- s_mode <= '1'; +-- s_validin <= '1'; +-- s_datain <= c_variable_plaintext_known_answers(index); +-- end loop; +-- wait until rising_edge(s_clk); +-- s_mode <= '0'; +-- s_validin <= '0'; +-- s_key <= (others => '0'); +-- s_datain <= (others => '0'); +-- wait for 100 ns; +-- -- Initial permutation known answer test +-- s_key <= x"0101010101010101"; +-- s_datain <= x"8000000000000000"; +-- for index in c_variable_plaintext_known_answers'range loop +-- wait until rising_edge(s_clk); +-- s_mode <= '1'; +-- s_validin <= '1'; +-- if(index /= 0) then +-- s_datain <= '0' & s_datain(0 to 62); +-- end if; +-- end loop; +-- wait until rising_edge(s_clk); +-- s_mode <= '0'; +-- s_validin <= '0'; +-- s_key <= (others => '0'); +-- s_datain <= (others => '0'); +-- -- Variable key known answer test +-- s_key <= x"8000000000000000"; +-- for index in c_variable_key_known_answers'range loop +-- wait until rising_edge(s_clk); +-- s_mode <= '1'; +-- s_validin <= '1'; +-- s_datain <= c_variable_key_known_answers(index); +-- if(index /= 0) then +-- if(index = 7 or index = 14 or index = 21 or index = 28 or index = 35 or +-- index = 42 or index = 49) then +-- s_key <= "00" & s_key(0 to 61); +-- else +-- s_key <= '0' & s_key(0 to 62); +-- end if; +-- end if; +-- end loop; +-- wait until rising_edge(s_clk); +-- s_mode <= '0'; +-- s_validin <= '0'; +-- s_key <= (others => '0'); +-- s_datain <= (others => '0'); +-- wait for 100 ns; +-- -- Permutation operation known answer test +-- for index in c_permutation_operation_known_answers_keys'range loop +-- wait until rising_edge(s_clk); +-- s_mode <= '1'; +-- s_validin <= '1'; +-- s_datain <= c_permutation_operation_known_answers_cipher(index); +-- s_key <= c_permutation_operation_known_answers_keys(index); +-- end loop; +-- wait until rising_edge(s_clk); +-- s_mode <= '0'; +-- s_validin <= '0'; +-- s_key <= (others => '0'); +-- s_datain <= (others => '0'); +-- wait for 100 ns; +-- -- Substitution table known answer test +-- for index in c_substitution_table_test_keys'range loop +-- wait until rising_edge(s_clk); +-- s_mode <= '1'; +-- s_validin <= '1'; +-- s_key <= c_substitution_table_test_keys(index); +-- s_datain <= c_substitution_table_test_cipher(index); +-- end loop; +-- wait until rising_edge(s_clk); +-- s_mode <= '0'; +-- s_validin <= '0'; +-- s_key <= (others => '0'); +-- s_datain <= (others => '0'); + wait; + end process teststimuliP; + + + testcheckerP : process is + variable v_plaintext : std_logic_vector(0 to 63) := x"8000000000000000"; + begin + report "# ENCRYPTION TESTS"; + report "# Variable plaintext known answer test"; + for index in c_variable_plaintext_known_answers'range loop + wait until rising_edge(s_clk) and s_validout = '1'; + assert (s_dataout = c_variable_plaintext_known_answers(index)) + report "encryption error" + severity error; + end loop; +-- report "# Inverse permutation known answer test"; +-- for index in c_variable_plaintext_known_answers'range loop +-- wait until rising_edge(s_clk) and s_validout = '1'; +-- assert (s_dataout = v_plaintext) +-- report "encryption error" +-- severity error; +-- v_plaintext := '0' & v_plaintext(0 to 62); +-- end loop; +-- report "# Variable key known answer test"; +-- for index in c_variable_key_known_answers'range loop +-- wait until rising_edge(s_clk) and s_validout = '1'; +-- assert (s_dataout = c_variable_key_known_answers(index)) +-- report "encryption error" +-- severity error; +-- end loop; +-- report "# Permutation operation known answer test"; +-- for index in c_permutation_operation_known_answers_cipher'range loop +-- wait until rising_edge(s_clk) and s_validout = '1'; +-- assert (s_dataout = c_permutation_operation_known_answers_cipher(index)) +-- report "encryption error" +-- severity error; +-- end loop; +-- report "# Substitution table known answer test"; +-- for index in c_substitution_table_test_cipher'range loop +-- wait until rising_edge(s_clk) and s_validout = '1'; +-- assert (s_dataout = c_substitution_table_test_cipher(index)) +-- report "encryption error" +-- severity error; +-- end loop; +-- report "# DECRYPTION TESTS"; +-- report "# Variable ciphertext known answer test"; +-- v_plaintext := x"8000000000000000"; +-- for index in c_variable_plaintext_known_answers'range loop +-- wait until rising_edge(s_clk) and s_validout = '1'; +-- assert (s_dataout = v_plaintext) +-- report "decryption error" +-- severity error; +-- v_plaintext := '0' & v_plaintext(0 to 62); +-- end loop; +-- report "# Initial permutation known answer test"; +-- for index in c_variable_plaintext_known_answers'range loop +-- wait until rising_edge(s_clk) and s_validout = '1'; +-- assert (s_dataout = c_variable_plaintext_known_answers(index)) +-- report "decryption error" +-- severity error; +-- end loop; +-- report "# Variable key known answer test"; +-- for index in c_variable_key_known_answers'range loop +-- wait until rising_edge(s_clk) and s_validout = '1'; +-- assert (s_dataout = x"0000000000000000") +-- report "decryption error" +-- severity error; +-- end loop; +-- report "# Permutation operation known answer test"; +-- for index in c_permutation_operation_known_answers_keys'range loop +-- wait until rising_edge(s_clk) and s_validout = '1'; +-- assert (s_dataout = x"0000000000000000") +-- report "decryption error" +-- severity error; +-- end loop; +-- report "# Substitution table known answer test"; +-- for index in c_substitution_table_test_cipher'range loop +-- wait until rising_edge(s_clk) and s_validout = '1'; +-- assert (s_dataout = c_substitution_table_test_plain(index)) +-- report "decryption error" +-- severity error; +-- end loop; + report "# Successfully passed all tests"; + wait; + end process testcheckerP; + + + i_cbcdes : cbcdes + port map ( + reset_i => s_reset, + clk_i => s_clk, + start_i => s_start, + mode_i => s_mode, + key_i => s_key, + iv_i => s_iv, + data_i => s_datain, + valid_i => s_validin, + ready_o => s_ready, + data_o => s_dataout, + valid_o => s_validout + ); + + +end architecture rtl;