diff --git a/tdes/sim/verilog/tb_tdes.v b/tdes/sim/verilog/tb_tdes.v
index 1320b8a..e97cfca 100644
--- a/tdes/sim/verilog/tb_tdes.v
+++ b/tdes/sim/verilog/tb_tdes.v
@@ -88,6 +88,7 @@ module tb_tdes;
   initial
     forever @(negedge reset) begin
       index = 0;
+      wait (reset);
       while (index < 19) begin
         @(posedge clk)
           if (ready) begin