From 5c74abc86ff808b3808ea80183fdf42f6e4015f9 Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Mon, 7 Jul 2014 12:28:11 +0200
Subject: [PATCH] added wait for disactivated reset before running testcases

---
 tdes/sim/verilog/tb_tdes.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tdes/sim/verilog/tb_tdes.v b/tdes/sim/verilog/tb_tdes.v
index 1320b8a..e97cfca 100644
--- a/tdes/sim/verilog/tb_tdes.v
+++ b/tdes/sim/verilog/tb_tdes.v
@@ -88,6 +88,7 @@ module tb_tdes;
   initial
     forever @(negedge reset) begin
       index = 0;
+      wait (reset);
       while (index < 19) begin
         @(posedge clk)
           if (ready) begin