diff --git a/des/rtl/des.vhd b/des/rtl/des.vhd index e40b4d7..ad7bbdd 100644 --- a/des/rtl/des.vhd +++ b/des/rtl/des.vhd @@ -50,95 +50,95 @@ BEGIN crypt : PROCESS ( clk_i ) IS -- variables for key calculation - VARIABLE c0 : std_logic_vector(0 TO 27); - VARIABLE c1 : std_logic_vector(0 TO 27); - VARIABLE c2 : std_logic_vector(0 TO 27); - VARIABLE c3 : std_logic_vector(0 TO 27); - VARIABLE c4 : std_logic_vector(0 TO 27); - VARIABLE c5 : std_logic_vector(0 TO 27); - VARIABLE c6 : std_logic_vector(0 TO 27); - VARIABLE c7 : std_logic_vector(0 TO 27); - VARIABLE c8 : std_logic_vector(0 TO 27); - VARIABLE c9 : std_logic_vector(0 TO 27); - VARIABLE c10 : std_logic_vector(0 TO 27); - VARIABLE c11 : std_logic_vector(0 TO 27); - VARIABLE c12 : std_logic_vector(0 TO 27); - VARIABLE c13 : std_logic_vector(0 TO 27); - VARIABLE c14 : std_logic_vector(0 TO 27); - VARIABLE c15 : std_logic_vector(0 TO 27); - VARIABLE c16 : std_logic_vector(0 TO 27); - VARIABLE d0 : std_logic_vector(0 TO 27); - VARIABLE d1 : std_logic_vector(0 TO 27); - VARIABLE d2 : std_logic_vector(0 TO 27); - VARIABLE d3 : std_logic_vector(0 TO 27); - VARIABLE d4 : std_logic_vector(0 TO 27); - VARIABLE d5 : std_logic_vector(0 TO 27); - VARIABLE d6 : std_logic_vector(0 TO 27); - VARIABLE d7 : std_logic_vector(0 TO 27); - VARIABLE d8 : std_logic_vector(0 TO 27); - VARIABLE d9 : std_logic_vector(0 TO 27); - VARIABLE d10 : std_logic_vector(0 TO 27); - VARIABLE d11 : std_logic_vector(0 TO 27); - VARIABLE d12 : std_logic_vector(0 TO 27); - VARIABLE d13 : std_logic_vector(0 TO 27); - VARIABLE d14 : std_logic_vector(0 TO 27); - VARIABLE d15 : std_logic_vector(0 TO 27); - VARIABLE d16 : std_logic_vector(0 TO 27); + VARIABLE c0 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c1 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c2 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c3 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c4 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c5 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c6 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c7 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c8 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c9 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d0 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d1 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d2 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d3 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d4 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d5 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d6 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d7 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d8 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d9 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0'); + VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0'); -- key variables - VARIABLE key1 : std_logic_vector(0 TO 47); - VARIABLE key2 : std_logic_vector(0 TO 47); - VARIABLE key3 : std_logic_vector(0 TO 47); - VARIABLE key4 : std_logic_vector(0 TO 47); - VARIABLE key5 : std_logic_vector(0 TO 47); - VARIABLE key6 : std_logic_vector(0 TO 47); - VARIABLE key7 : std_logic_vector(0 TO 47); - VARIABLE key8 : std_logic_vector(0 TO 47); - VARIABLE key9 : std_logic_vector(0 TO 47); - VARIABLE key10 : std_logic_vector(0 TO 47); - VARIABLE key11 : std_logic_vector(0 TO 47); - VARIABLE key12 : std_logic_vector(0 TO 47); - VARIABLE key13 : std_logic_vector(0 TO 47); - VARIABLE key14 : std_logic_vector(0 TO 47); - VARIABLE key15 : std_logic_vector(0 TO 47); - VARIABLE key16 : std_logic_vector(0 TO 47); + VARIABLE key1 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key2 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key3 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key4 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key5 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key6 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key7 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key8 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key9 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0'); + VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0'); -- variables for left & right data blocks - VARIABLE l0 : std_logic_vector( 0 TO 31); - VARIABLE l1 : std_logic_vector( 0 TO 31); - VARIABLE l2 : std_logic_vector( 0 TO 31); - VARIABLE l3 : std_logic_vector( 0 TO 31); - VARIABLE l4 : std_logic_vector( 0 TO 31); - VARIABLE l5 : std_logic_vector( 0 TO 31); - VARIABLE l6 : std_logic_vector( 0 TO 31); - VARIABLE l7 : std_logic_vector( 0 TO 31); - VARIABLE l8 : std_logic_vector( 0 TO 31); - VARIABLE l9 : std_logic_vector( 0 TO 31); - VARIABLE l10 : std_logic_vector( 0 TO 31); - VARIABLE l11 : std_logic_vector( 0 TO 31); - VARIABLE l12 : std_logic_vector( 0 TO 31); - VARIABLE l13 : std_logic_vector( 0 TO 31); - VARIABLE l14 : std_logic_vector( 0 TO 31); - VARIABLE l15 : std_logic_vector( 0 TO 31); - VARIABLE l16 : std_logic_vector( 0 TO 31); - VARIABLE r0 : std_logic_vector( 0 TO 31); - VARIABLE r1 : std_logic_vector( 0 TO 31); - VARIABLE r2 : std_logic_vector( 0 TO 31); - VARIABLE r3 : std_logic_vector( 0 TO 31); - VARIABLE r4 : std_logic_vector( 0 TO 31); - VARIABLE r5 : std_logic_vector( 0 TO 31); - VARIABLE r6 : std_logic_vector( 0 TO 31); - VARIABLE r7 : std_logic_vector( 0 TO 31); - VARIABLE r8 : std_logic_vector( 0 TO 31); - VARIABLE r9 : std_logic_vector( 0 TO 31); - VARIABLE r10 : std_logic_vector( 0 TO 31); - VARIABLE r11 : std_logic_vector( 0 TO 31); - VARIABLE r12 : std_logic_vector( 0 TO 31); - VARIABLE r13 : std_logic_vector( 0 TO 31); - VARIABLE r14 : std_logic_vector( 0 TO 31); - VARIABLE r15 : std_logic_vector( 0 TO 31); - VARIABLE r16 : std_logic_vector( 0 TO 31); + VARIABLE l0 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l1 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l2 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l3 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l4 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l5 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l6 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l7 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l8 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l9 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r0 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r1 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r2 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r3 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r4 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r5 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r6 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r7 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r8 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r9 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0'); + VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0'); -- variables for mode & valid shift registers - VARIABLE mode : std_logic_vector(0 TO 16); - VARIABLE valid : std_logic_vector(0 TO 17); + VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0'); + VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0'); BEGIN IF rising_edge( clk_i ) THEN -- shift registers @@ -333,4 +333,4 @@ BEGIN END IF; END PROCESS crypt; -END ARCHITECTURE rtl; \ No newline at end of file +END ARCHITECTURE rtl;