From 734efbc59f49e504e00b171ca4c019e2a7284dc9 Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Fri, 22 Mar 2013 23:23:30 +0100
Subject: [PATCH] added test cases for decryption in stimuli & checker; bugfix
 wwith validout detection

---
 des/sim/verilog/tb_des.v | 119 +++++++++++++++++++++++++++++----------
 1 file changed, 88 insertions(+), 31 deletions(-)

diff --git a/des/sim/verilog/tb_des.v b/des/sim/verilog/tb_des.v
index 7d9d09c..6805fa9 100644
--- a/des/sim/verilog/tb_des.v
+++ b/des/sim/verilog/tb_des.v
@@ -21,14 +21,17 @@
 `timescale 1ns/1ps
 
 
+
 module tb_des;
 
+
   // set dumpfile
   initial begin
      $dumpfile ("tb_des.vcd");
      $dumpvars (0, tb_des);
   end
 
+
   reg reset;
   reg clk = 0;
   reg mode;
@@ -37,13 +40,15 @@ module tb_des;
   reg validin;
   integer index;
   integer outdex;
-  integer errors;
+  integer enc_errors;
+  integer dec_errors;
   wire [0:63] dataout;
   wire validout;
 
-  reg [0:63] data_input  [0:127];
-  reg [0:63] key_input   [0:127];
-  reg [0:63] data_output [0:127];
+  reg [0:63] data_input  [0:469];
+  reg [0:63] key_input   [0:469];
+  reg [0:63] data_output [0:469];
+
 
   // read in test data files
   initial begin
@@ -52,72 +57,124 @@ module tb_des;
     $readmemh("data_output.txt", data_output);
   end
 
+
   // setup simulation
   initial begin
     reset = 1;
     #1  reset = 0;
     #20 reset = 1;
-    #2000 $finish;
   end
 
+
   // generate clock with 100 mhz
   always #5 clk = !clk;
 
+
   // init the register values
   initial
     forever @(negedge reset) begin
-      disable stimuli;
+      //disable stimuli;
       disable checker;
-      mode    <= 0;
-      validin <= 0;
-      key     <= 0;
-      datain  <= 0;
-      errors  =  0;
+      mode       <= 0;
+      validin    <= 0;
+      key        <= 0;
+      datain     <= 0;
+      enc_errors =  0;
+      dec_errors =  0;
     end
 
+
    // stimuli generator process
-  always begin : stimuli
-    wait (reset)
-    @(posedge clk)
-      // Variable plaintext known answer test
-      for(index = 0; index < 128; index = index + 1)
-      begin
+  initial
+    forever @(negedge reset) begin
+      @(posedge clk)
+        for (index = 0; index < 235; index = index + 1)
+        begin
+          @(posedge clk)
+            mode    <= 0;
+            validin <= 1;
+            datain  <= data_input[index];
+            key     <= key_input[index];
+        end
+        for (index = 0; index < 10; index = index + 1)
+        begin
+          @(posedge clk)
+            validin <= 0;
+        end
+        for (index = 235; index < 470; index = index + 1)
+        begin
+          @(posedge clk)
+            mode    <= 1;
+            validin <= 1;
+            datain  <= data_input[index];
+            key     <= key_input[index];
+        end
         @(posedge clk)
+          validin <= 0;
           mode    <= 0;
-          validin <= 1;
-          datain  <= data_input[index];
-          key     <= key_input[index];
-      end
-      validin <= 0;
-  end
+    end
+
 
   // checker process
   always begin : checker
+
     wait (reset)
-    // Variable plaintext known answer test
-    wait (validout)
-    for(outdex = 0; outdex < 128; outdex = outdex + 1)
+
+    // encryption tests
+    @(posedge validout)
+    for(outdex = 0; outdex < 235; outdex = outdex + 1)
     begin
       @(posedge clk)
       // detected an error -> print error message
-      // increent error counter
+      // increment error counter
       if (dataout != data_output[outdex]) begin
         $display ("error, output was %h - should have been %h", dataout, data_output[outdex]);
-        errors = errors + 1;
+        enc_errors = enc_errors + 1;
       end
     end
+
     // simulation finished -> print messages and if an error was detected
     $display   ("#############");
-    if (errors) begin
-      $display ("test finished, %0d errors detected :(", errors);
+    if (enc_errors) begin
+      $display ("encryption tests finished, %0d errors detected :(", enc_errors);
     end else begin
-      $display ("test finished, no errors detected :)");
+      $display ("encryption tests finished, no errors detected :)");
     end
+
+    // decryption tests
+    @(posedge validout)
+    for(outdex = 235; outdex < 470; outdex = outdex + 1)
+    begin
+      @(posedge clk)
+      // detected an error -> print error message
+      // increment error counter
+       if (dataout != data_output[outdex]) begin
+         $display ("error, output was %h - should have been %h", dataout, data_output[outdex]);
+         dec_errors = dec_errors + 1;
+       end
+    end
+
+    // simulation finished -> print messages and if an error was detected
     $display   ("#############");
+    if (dec_errors) begin
+      $display ("decryption tests finished, %0d errors detected :(", dec_errors);
+    end else begin
+      $display ("decryption tests finished, no errors detected :)");
+    end
+    $display   ("#############");
+
+    if (dec_errors | enc_errors) begin
+      $display ("simulation finished, %0d errors detected :(", enc_errors + dec_errors);
+    end else begin
+      $display ("simulation tests finished, no errors detected :)");
+    end
+    $display ("#############");
+
     @(posedge clk)
       $finish;
   end
 
+
   // dut
   des i_des (
     .reset_i(reset),