diff --git a/des/rtl/vhdl/des.vhd b/des/rtl/vhdl/des.vhd index 7e3e986..838f6a1 100644 --- a/des/rtl/vhdl/des.vhd +++ b/des/rtl/vhdl/des.vhd @@ -32,15 +32,15 @@ entity des is ); port ( reset_i : in std_logic; -- async reset - clk_i : IN std_logic; -- clock - mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt - key_i : IN std_logic_vector(0 TO 63); -- key input - data_i : IN std_logic_vector(0 TO 63); -- data input - valid_i : IN std_logic; -- input key/data valid - accept_o : out std_logic; -- input data accepted - data_o : OUT std_logic_vector(0 TO 63); -- data output - valid_o : OUT std_logic; -- output data valid flag - accept_i : in std_logic + clk_i : in std_logic; -- clock + mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt + key_i : in std_logic_vector(0 to 63); -- key input + data_i : in std_logic_vector(0 to 63); -- data input + valid_i : in std_logic; -- input key/data valid + accept_o : out std_logic; -- input accept + data_o : out std_logic_vector(0 to 63); -- data output + valid_o : out std_logic; -- output data valid flag + accept_i : in std_logic -- output accept ); end entity des; @@ -56,294 +56,294 @@ begin begin - crypt : PROCESS (clk_i, reset_i) IS + crypt : process (clk_i, reset_i) is -- variables for key calculation - VARIABLE c0 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c1 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c2 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c3 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c4 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c5 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c6 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c7 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c8 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c9 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d0 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d1 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d2 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d3 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d4 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d5 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d6 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d7 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d8 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d9 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0'); + variable c0 : std_logic_vector(0 to 27) := (others => '0'); + variable c1 : std_logic_vector(0 to 27) := (others => '0'); + variable c2 : std_logic_vector(0 to 27) := (others => '0'); + variable c3 : std_logic_vector(0 to 27) := (others => '0'); + variable c4 : std_logic_vector(0 to 27) := (others => '0'); + variable c5 : std_logic_vector(0 to 27) := (others => '0'); + variable c6 : std_logic_vector(0 to 27) := (others => '0'); + variable c7 : std_logic_vector(0 to 27) := (others => '0'); + variable c8 : std_logic_vector(0 to 27) := (others => '0'); + variable c9 : std_logic_vector(0 to 27) := (others => '0'); + variable c10 : std_logic_vector(0 to 27) := (others => '0'); + variable c11 : std_logic_vector(0 to 27) := (others => '0'); + variable c12 : std_logic_vector(0 to 27) := (others => '0'); + variable c13 : std_logic_vector(0 to 27) := (others => '0'); + variable c14 : std_logic_vector(0 to 27) := (others => '0'); + variable c15 : std_logic_vector(0 to 27) := (others => '0'); + variable c16 : std_logic_vector(0 to 27) := (others => '0'); + variable d0 : std_logic_vector(0 to 27) := (others => '0'); + variable d1 : std_logic_vector(0 to 27) := (others => '0'); + variable d2 : std_logic_vector(0 to 27) := (others => '0'); + variable d3 : std_logic_vector(0 to 27) := (others => '0'); + variable d4 : std_logic_vector(0 to 27) := (others => '0'); + variable d5 : std_logic_vector(0 to 27) := (others => '0'); + variable d6 : std_logic_vector(0 to 27) := (others => '0'); + variable d7 : std_logic_vector(0 to 27) := (others => '0'); + variable d8 : std_logic_vector(0 to 27) := (others => '0'); + variable d9 : std_logic_vector(0 to 27) := (others => '0'); + variable d10 : std_logic_vector(0 to 27) := (others => '0'); + variable d11 : std_logic_vector(0 to 27) := (others => '0'); + variable d12 : std_logic_vector(0 to 27) := (others => '0'); + variable d13 : std_logic_vector(0 to 27) := (others => '0'); + variable d14 : std_logic_vector(0 to 27) := (others => '0'); + variable d15 : std_logic_vector(0 to 27) := (others => '0'); + variable d16 : std_logic_vector(0 to 27) := (others => '0'); -- key variables - VARIABLE key1 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key2 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key3 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key4 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key5 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key6 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key7 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key8 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key9 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0'); + variable key1 : std_logic_vector(0 to 47) := (others => '0'); + variable key2 : std_logic_vector(0 to 47) := (others => '0'); + variable key3 : std_logic_vector(0 to 47) := (others => '0'); + variable key4 : std_logic_vector(0 to 47) := (others => '0'); + variable key5 : std_logic_vector(0 to 47) := (others => '0'); + variable key6 : std_logic_vector(0 to 47) := (others => '0'); + variable key7 : std_logic_vector(0 to 47) := (others => '0'); + variable key8 : std_logic_vector(0 to 47) := (others => '0'); + variable key9 : std_logic_vector(0 to 47) := (others => '0'); + variable key10 : std_logic_vector(0 to 47) := (others => '0'); + variable key11 : std_logic_vector(0 to 47) := (others => '0'); + variable key12 : std_logic_vector(0 to 47) := (others => '0'); + variable key13 : std_logic_vector(0 to 47) := (others => '0'); + variable key14 : std_logic_vector(0 to 47) := (others => '0'); + variable key15 : std_logic_vector(0 to 47) := (others => '0'); + variable key16 : std_logic_vector(0 to 47) := (others => '0'); -- variables for left & right data blocks - VARIABLE l0 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l1 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l2 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l3 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l4 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l5 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l6 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l7 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l8 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l9 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r0 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r1 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r2 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r3 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r4 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r5 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r6 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r7 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r8 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r9 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0'); + variable l0 : std_logic_vector( 0 to 31) := (others => '0'); + variable l1 : std_logic_vector( 0 to 31) := (others => '0'); + variable l2 : std_logic_vector( 0 to 31) := (others => '0'); + variable l3 : std_logic_vector( 0 to 31) := (others => '0'); + variable l4 : std_logic_vector( 0 to 31) := (others => '0'); + variable l5 : std_logic_vector( 0 to 31) := (others => '0'); + variable l6 : std_logic_vector( 0 to 31) := (others => '0'); + variable l7 : std_logic_vector( 0 to 31) := (others => '0'); + variable l8 : std_logic_vector( 0 to 31) := (others => '0'); + variable l9 : std_logic_vector( 0 to 31) := (others => '0'); + variable l10 : std_logic_vector( 0 to 31) := (others => '0'); + variable l11 : std_logic_vector( 0 to 31) := (others => '0'); + variable l12 : std_logic_vector( 0 to 31) := (others => '0'); + variable l13 : std_logic_vector( 0 to 31) := (others => '0'); + variable l14 : std_logic_vector( 0 to 31) := (others => '0'); + variable l15 : std_logic_vector( 0 to 31) := (others => '0'); + variable l16 : std_logic_vector( 0 to 31) := (others => '0'); + variable r0 : std_logic_vector( 0 to 31) := (others => '0'); + variable r1 : std_logic_vector( 0 to 31) := (others => '0'); + variable r2 : std_logic_vector( 0 to 31) := (others => '0'); + variable r3 : std_logic_vector( 0 to 31) := (others => '0'); + variable r4 : std_logic_vector( 0 to 31) := (others => '0'); + variable r5 : std_logic_vector( 0 to 31) := (others => '0'); + variable r6 : std_logic_vector( 0 to 31) := (others => '0'); + variable r7 : std_logic_vector( 0 to 31) := (others => '0'); + variable r8 : std_logic_vector( 0 to 31) := (others => '0'); + variable r9 : std_logic_vector( 0 to 31) := (others => '0'); + variable r10 : std_logic_vector( 0 to 31) := (others => '0'); + variable r11 : std_logic_vector( 0 to 31) := (others => '0'); + variable r12 : std_logic_vector( 0 to 31) := (others => '0'); + variable r13 : std_logic_vector( 0 to 31) := (others => '0'); + variable r14 : std_logic_vector( 0 to 31) := (others => '0'); + variable r15 : std_logic_vector( 0 to 31) := (others => '0'); + variable r16 : std_logic_vector( 0 to 31) := (others => '0'); -- variables for mode & valid shift registers - VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0'); - VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0'); - BEGIN + variable mode : std_logic_vector(0 to 16) := (others => '0'); + variable valid : std_logic_vector(0 to 17) := (others => '0'); + begin if(reset_i = '0') then data_o <= (others => '0'); valid_o <= '0'; - elsif rising_edge( clk_i ) THEN + elsif rising_edge( clk_i ) then -- shift registers - valid(1 TO 17) := valid(0 TO 16); + valid(1 to 17) := valid(0 to 16); valid(0) := valid_i; - mode(1 TO 16) := mode(0 TO 15); + mode(1 to 16) := mode(0 to 15); mode(0) := mode_i; -- output stage accept_o <= '1'; valid_o <= valid(17); data_o <= ipn( ( r16 & l16 ) ); -- 16. stage - IF mode(16) = '0' THEN - c16 := c15(1 TO 27) & c15(0); - d16 := d15(1 TO 27) & d15(0); - ELSE - c16 := c15(27) & c15(0 TO 26); - d16 := d15(27) & d15(0 TO 26); - END IF; + if mode(16) = '0' then + c16 := c15(1 to 27) & c15(0); + d16 := d15(1 to 27) & d15(0); + else + c16 := c15(27) & c15(0 to 26); + d16 := d15(27) & d15(0 to 26); + end if; key16 := pc2( ( c16 & d16 ) ); l16 := r15; r16 := l15 xor ( f( r15, key16 ) ); -- 15. stage - IF mode(15) = '0' THEN - c15 := c14(2 TO 27) & c14(0 TO 1); - d15 := d14(2 TO 27) & d14(0 TO 1); - ELSE - c15 := c14(26 TO 27) & c14(0 TO 25); - d15 := d14(26 TO 27) & d14(0 TO 25); - END IF; + if mode(15) = '0' then + c15 := c14(2 to 27) & c14(0 to 1); + d15 := d14(2 to 27) & d14(0 to 1); + else + c15 := c14(26 to 27) & c14(0 to 25); + d15 := d14(26 to 27) & d14(0 to 25); + end if; key15 := pc2( ( c15 & d15 ) ); l15 := r14; r15 := l14 xor ( f( r14, key15 ) ); -- 14. stage - IF mode(14) = '0' THEN - c14 := c13(2 TO 27) & c13(0 TO 1); - d14 := d13(2 TO 27) & d13(0 TO 1); - ELSE - c14 := c13(26 TO 27) & c13(0 TO 25); - d14 := d13(26 TO 27) & d13(0 TO 25); - END IF; + if mode(14) = '0' then + c14 := c13(2 to 27) & c13(0 to 1); + d14 := d13(2 to 27) & d13(0 to 1); + else + c14 := c13(26 to 27) & c13(0 to 25); + d14 := d13(26 to 27) & d13(0 to 25); + end if; key14 := pc2( ( c14 & d14 ) ); l14 := r13; r14 := l13 xor ( f( r13, key14 ) ); -- 13. stage - IF mode(13) = '0' THEN - c13 := c12(2 TO 27) & c12(0 TO 1); - d13 := d12(2 TO 27) & d12(0 TO 1); - ELSE - c13 := c12(26 TO 27) & c12(0 TO 25); - d13 := d12(26 TO 27) & d12(0 TO 25); - END IF; + if mode(13) = '0' then + c13 := c12(2 to 27) & c12(0 to 1); + d13 := d12(2 to 27) & d12(0 to 1); + else + c13 := c12(26 to 27) & c12(0 to 25); + d13 := d12(26 to 27) & d12(0 to 25); + end if; key13 := pc2( ( c13 & d13 ) ); l13 := r12; r13 := l12 xor ( f( r12, key13 ) ); -- 12. stage - IF mode(12) = '0' THEN - c12 := c11(2 TO 27) & c11(0 TO 1); - d12 := d11(2 TO 27) & d11(0 TO 1); - ELSE - c12 := c11(26 TO 27) & c11(0 TO 25); - d12 := d11(26 TO 27) & d11(0 TO 25); - END IF; + if mode(12) = '0' then + c12 := c11(2 to 27) & c11(0 to 1); + d12 := d11(2 to 27) & d11(0 to 1); + else + c12 := c11(26 to 27) & c11(0 to 25); + d12 := d11(26 to 27) & d11(0 to 25); + end if; key12 := pc2( ( c12 & d12 ) ); l12 := r11; r12 := l11 xor ( f( r11, key12 ) ); -- 11. stage - IF mode(11) = '0' THEN - c11 := c10(2 TO 27) & c10(0 TO 1); - d11 := d10(2 TO 27) & d10(0 TO 1); - ELSE - c11 := c10(26 TO 27) & c10(0 TO 25); - d11 := d10(26 TO 27) & d10(0 TO 25); - END IF; + if mode(11) = '0' then + c11 := c10(2 to 27) & c10(0 to 1); + d11 := d10(2 to 27) & d10(0 to 1); + else + c11 := c10(26 to 27) & c10(0 to 25); + d11 := d10(26 to 27) & d10(0 to 25); + end if; key11 := pc2( ( c11 & d11 ) ); l11 := r10; r11 := l10 xor ( f( r10, key11 ) ); -- 10. stage - IF mode(10) = '0' THEN - c10 := c9(2 TO 27) & c9(0 TO 1); - d10 := d9(2 TO 27) & d9(0 TO 1); - ELSE - c10 := c9(26 TO 27) & c9(0 TO 25); - d10 := d9(26 TO 27) & d9(0 TO 25); - END IF; + if mode(10) = '0' then + c10 := c9(2 to 27) & c9(0 to 1); + d10 := d9(2 to 27) & d9(0 to 1); + else + c10 := c9(26 to 27) & c9(0 to 25); + d10 := d9(26 to 27) & d9(0 to 25); + end if; key10 := pc2( ( c10 & d10 ) ); l10 := r9; r10 := l9 xor ( f( r9, key10 ) ); -- 9. stage - IF mode(9) = '0' THEN - c9 := c8(1 TO 27) & c8(0); - d9 := d8(1 TO 27) & d8(0); - ELSE - c9 := c8(27) & c8(0 TO 26); - d9 := d8(27) & d8(0 TO 26); - END IF; + if mode(9) = '0' then + c9 := c8(1 to 27) & c8(0); + d9 := d8(1 to 27) & d8(0); + else + c9 := c8(27) & c8(0 to 26); + d9 := d8(27) & d8(0 to 26); + end if; key9 := pc2( ( c9 & d9 ) ); l9 := r8; r9 := l8 xor ( f( r8, key9 ) ); -- 8. stage - IF mode(8) = '0' THEN - c8 := c7(2 TO 27) & c7(0 TO 1); - d8 := d7(2 TO 27) & d7(0 TO 1); - ELSE - c8 := c7(26 TO 27) & c7(0 TO 25); - d8 := d7(26 TO 27) & d7(0 TO 25); - END IF; + if mode(8) = '0' then + c8 := c7(2 to 27) & c7(0 to 1); + d8 := d7(2 to 27) & d7(0 to 1); + else + c8 := c7(26 to 27) & c7(0 to 25); + d8 := d7(26 to 27) & d7(0 to 25); + end if; key8 := pc2( ( c8 & d8 ) ); l8 := r7; r8 := l7 xor ( f( r7, key8 ) ); -- 7. stage - IF mode(7) = '0' THEN - c7 := c6(2 TO 27) & c6(0 TO 1); - d7 := d6(2 TO 27) & d6(0 TO 1); - ELSE - c7 := c6(26 TO 27) & c6(0 TO 25); - d7 := d6(26 TO 27) & d6(0 TO 25); - END IF; + if mode(7) = '0' then + c7 := c6(2 to 27) & c6(0 to 1); + d7 := d6(2 to 27) & d6(0 to 1); + else + c7 := c6(26 to 27) & c6(0 to 25); + d7 := d6(26 to 27) & d6(0 to 25); + end if; key7 := pc2( ( c7 & d7 ) ); l7 := r6; r7 := l6 xor ( f( r6, key7 ) ); -- 6. stage - IF mode(6) = '0' THEN - c6 := c5(2 TO 27) & c5(0 TO 1); - d6 := d5(2 TO 27) & d5(0 TO 1); - ELSE - c6 := c5(26 TO 27) & c5(0 TO 25); - d6 := d5(26 TO 27) & d5(0 TO 25); - END IF; + if mode(6) = '0' then + c6 := c5(2 to 27) & c5(0 to 1); + d6 := d5(2 to 27) & d5(0 to 1); + else + c6 := c5(26 to 27) & c5(0 to 25); + d6 := d5(26 to 27) & d5(0 to 25); + end if; key6 := pc2( ( c6 & d6 ) ); l6 := r5; r6 := l5 xor ( f( r5, key6 ) ); -- 5. stage - IF mode(5) = '0' THEN - c5 := c4(2 TO 27) & c4(0 TO 1); - d5 := d4(2 TO 27) & d4(0 TO 1); - ELSE - c5 := c4(26 TO 27) & c4(0 TO 25); - d5 := d4(26 TO 27) & d4(0 TO 25); - END IF; + if mode(5) = '0' then + c5 := c4(2 to 27) & c4(0 to 1); + d5 := d4(2 to 27) & d4(0 to 1); + else + c5 := c4(26 to 27) & c4(0 to 25); + d5 := d4(26 to 27) & d4(0 to 25); + end if; key5 := pc2( ( c5 & d5 ) ); l5 := r4; r5 := l4 xor ( f( r4, key5 ) ); -- 4. stage - IF mode(4) = '0' THEN - c4 := c3(2 TO 27) & c3(0 TO 1); - d4 := d3(2 TO 27) & d3(0 TO 1); - ELSE - c4 := c3(26 TO 27) & c3(0 TO 25); - d4 := d3(26 TO 27) & d3(0 TO 25); - END IF; + if mode(4) = '0' then + c4 := c3(2 to 27) & c3(0 to 1); + d4 := d3(2 to 27) & d3(0 to 1); + else + c4 := c3(26 to 27) & c3(0 to 25); + d4 := d3(26 to 27) & d3(0 to 25); + end if; key4 := pc2( ( c4 & d4 ) ); l4 := r3; r4 := l3 xor ( f( r3, key4 ) ); -- 3. stage - IF mode(3) = '0' THEN - c3 := c2(2 TO 27) & c2(0 TO 1); - d3 := d2(2 TO 27) & d2(0 TO 1); - ELSE - c3 := c2(26 TO 27) & c2(0 TO 25); - d3 := d2(26 TO 27) & d2(0 TO 25); - END IF; + if mode(3) = '0' then + c3 := c2(2 to 27) & c2(0 to 1); + d3 := d2(2 to 27) & d2(0 to 1); + else + c3 := c2(26 to 27) & c2(0 to 25); + d3 := d2(26 to 27) & d2(0 to 25); + end if; key3 := pc2( ( c3 & d3 ) ); l3 := r2; r3 := l2 xor ( f( r2, key3 ) ); -- 2. stage - IF mode(2) = '0' THEN - c2 := c1(1 TO 27) & c1(0); - d2 := d1(1 TO 27) & d1(0); - ELSE - c2 := c1(27) & c1(0 TO 26); - d2 := d1(27) & d1(0 TO 26); - END IF; + if mode(2) = '0' then + c2 := c1(1 to 27) & c1(0); + d2 := d1(1 to 27) & d1(0); + else + c2 := c1(27) & c1(0 to 26); + d2 := d1(27) & d1(0 to 26); + end if; key2 := pc2( ( c2 & d2 ) ); l2 := r1; r2 := l1 xor ( f( r1, key2 ) ); -- 1. stage - IF mode(1) = '0' THEN - c1 := c0(1 TO 27) & c0(0); - d1 := d0(1 TO 27) & d0(0); - ELSE + if mode(1) = '0' then + c1 := c0(1 to 27) & c0(0); + d1 := d0(1 to 27) & d0(0); + else c1 := c0; d1 := d0; - END IF; + end if; key1 := pc2( ( c1 & d1 ) ); l1 := r0; r1 := l0 xor ( f( r0, key1 ) ); -- input stage - l0 := ip( data_i )(0 TO 31); - r0 := ip( data_i )(32 TO 63); + l0 := ip( data_i )(0 to 31); + r0 := ip( data_i )(32 to 63); c0 := pc1_c( key_i ); d0 := pc1_d( key_i ); - END IF; - END PROCESS crypt; + end if; + end process crypt; end generate PipeG; @@ -358,7 +358,6 @@ begin begin - cryptP : process (clk_i, reset_i) is variable v_c : std_logic_vector(0 to 27); variable v_d : std_logic_vector(0 to 27); @@ -624,5 +623,4 @@ begin end generate AreaG; - -END ARCHITECTURE rtl; +end architecture rtl; diff --git a/des/rtl/vhdl/des_pkg.vhd b/des/rtl/vhdl/des_pkg.vhd index d485b64..5b3cef5 100644 --- a/des/rtl/vhdl/des_pkg.vhd +++ b/des/rtl/vhdl/des_pkg.vhd @@ -20,37 +20,16 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.numeric_std.ALL; +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; -PACKAGE des_pkg IS +package des_pkg is - FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - - FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; - FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; - - FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - - FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector; - - FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector; - - TYPE ip_matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63; + type ip_matrix is array (0 to 63) of natural range 0 to 63; constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17, 9, 1, 59, 51, 43, 35, 27, 19, 11, 3, 61, 53, 45, 37, 29, 21, 13, 5, @@ -68,7 +47,7 @@ PACKAGE des_pkg IS 33, 1, 41, 9, 49, 17, 57, 25, 32, 0, 40, 8, 48, 16, 56, 24); - TYPE e_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31; + type e_matrix is array (0 to 47) of natural range 0 to 31; constant e_table : e_matrix := (31, 0, 1, 2, 3, 4, 3, 4, 5, 6, 7, 8, 7, 8, 9, 10, 11, 12, @@ -78,7 +57,7 @@ PACKAGE des_pkg IS 23, 24, 25, 26, 27, 28, 27, 28, 29, 30, 31, 0); - TYPE s_matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; + type s_matrix is array (0 to 3, 0 to 15) of integer range 0 to 15; constant s1_table : s_matrix := (0 => (14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7), 1 => ( 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8), 2 => ( 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0), @@ -112,7 +91,7 @@ PACKAGE des_pkg IS 2 => ( 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8), 3 => ( 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11)); - type pc_matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63; + type pc_matrix is array (0 to 27) of natural range 0 to 63; constant pc1c_table : pc_matrix := (56, 48, 40, 32, 24, 16, 8, 0, 57, 49, 41, 33, 25, 17, 9, 1, 58, 50, 42, 34, 26, @@ -122,7 +101,7 @@ PACKAGE des_pkg IS 13, 5, 60, 52, 44, 36, 28, 20, 12, 4, 27, 19, 11, 3); - type p_matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31; + type p_matrix is array (0 to 31) of natural range 0 to 31; constant p_table : p_matrix := (15, 6, 19, 20, 28, 11, 27, 16, 0, 14, 22, 25, @@ -132,7 +111,7 @@ PACKAGE des_pkg IS 18, 12, 29, 5, 21, 10, 3, 24); - type pc2_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63; + type pc2_matrix is array (0 to 47) of natural range 0 to 63; constant pc2_table : pc2_matrix := (13, 16, 10, 23, 0, 4, 2, 27, 14, 5, 20, 9, 22, 18, 11, 3, 25, 7, @@ -142,191 +121,122 @@ PACKAGE des_pkg IS 43, 48, 38, 55, 33, 52, 45, 41, 49, 35, 28, 31); + function ip ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector; + function ipn ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector; + + function e (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector; + function p (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector; + + function s (input_vector : std_logic_vector(0 to 5); s_table : s_matrix ) return std_logic_vector; + + function f (input_r : std_logic_vector(0 to 31); input_key : std_logic_vector(0 to 47) ) return std_logic_vector; + + function pc1_c ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector; + function pc1_d ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector; + function pc2 ( input_vector : std_logic_vector(0 to 55) ) return std_logic_vector; + -END PACKAGE des_pkg; +end package des_pkg; -PACKAGE BODY des_pkg IS +package body des_pkg is - FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 63); - BEGIN - FOR index IN 0 TO 63 LOOP + function ip ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is + variable result : std_logic_vector(0 to 63); + begin + for index IN 0 to 63 loop result( index ) := input_vector( ip_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION ip; - - FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 63); - BEGIN - FOR index IN 0 TO 63 LOOP + end loop; + return result; + end function ip; + + + function ipn ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is + variable result : std_logic_vector(0 to 63); + begin + for index IN 0 to 63 loop result( index ) := input_vector( ipn_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION ipn; - - FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 47); - BEGIN - FOR index IN 0 TO 47 LOOP + end loop; + return result; + end function ipn; + + + function e (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector is + variable result : std_logic_vector(0 to 47); + begin + for index IN 0 to 47 loop result( index ) := input_vector( e_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION e; - - FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s1_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s1; - - FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s2_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s2; - - FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s3_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s3; - - FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s4_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s4; - - FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s5_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s5; - - FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s6_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s6; - - FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s7_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s7; - - FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN + end loop; + return result; + end function e; + + + function s ( input_vector : std_logic_vector(0 to 5); s_table : s_matrix ) return std_logic_vector is + variable int : std_logic_vector(0 to 1); + variable i : integer range 0 to 3; + variable j : integer range 0 to 15; + variable result : std_logic_vector(0 to 3); + begin int := input_vector( 0 ) & input_vector( 5 ); i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s8_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s8; - - FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 31); - BEGIN - FOR index IN 0 TO 31 LOOP + j := to_integer( unsigned( input_vector( 1 to 4) ) ); + result := std_logic_vector( to_unsigned( s_table( i, j ), 4 ) ); + return result; + end function s; + + + function p (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector is + variable result : std_logic_vector(0 to 31); + begin + for index IN 0 to 31 loop result( index ) := input_vector( p_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION p; - - FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS - VARIABLE intern : std_logic_vector(0 TO 47); - VARIABLE result : std_logic_vector(0 TO 31); - BEGIN + end loop; + return result; + end function p; + + + function f (input_r : std_logic_vector(0 to 31); input_key : std_logic_vector(0 to 47) ) return std_logic_vector is + variable intern : std_logic_vector(0 to 47); + variable result : std_logic_vector(0 to 31); + begin intern := e( input_r ) xor input_key; - result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) & - s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) ); - RETURN result; - END FUNCTION f; - - FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 27); - BEGIN - FOR index IN 0 TO 27 LOOP + result := p( s( intern(0 to 5), s1_table ) & s( intern(6 to 11), s2_table ) & s( intern(12 to 17), s3_table ) & + s( intern(18 to 23), s4_table ) & s( intern(24 to 29), s5_table ) & s( intern(30 to 35), s6_table ) & + s( intern(36 to 41), s7_table ) & s( intern(42 to 47), s8_table ) ); + return result; + end function f; + + + function pc1_c ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is + variable result : std_logic_vector(0 to 27); + begin + for index IN 0 to 27 loop result( index ) := input_vector( pc1c_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc1_c; + end loop; + return result; + end function pc1_c; - FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 27); - BEGIN - FOR index IN 0 TO 27 LOOP + function pc1_d ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is + variable result : std_logic_vector(0 to 27); + begin + for index IN 0 to 27 loop result( index ) := input_vector( pc1d_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc1_d; - - FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 47); - BEGIN - FOR index IN 0 TO 47 LOOP + end loop; + return result; + end function pc1_d; + + + function pc2 ( input_vector : std_logic_vector(0 to 55) ) return std_logic_vector is + variable result : std_logic_vector(0 to 47); + begin + for index IN 0 to 47 loop result( index ) := input_vector( pc2_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc2; + end loop; + return result; + end function pc2; -END PACKAGE BODY des_pkg; +end package body des_pkg;