From 8f2e24fb8ca1c42b4a72f0081e6b7527e8fbf758 Mon Sep 17 00:00:00 2001
From: Torsten Meissner <torsten@meissneronline.net>
Date: Sun, 25 Mar 2012 00:10:18 +0100
Subject: [PATCH] new verilog testbench, makefile & tcl-file

---
 des/sim/verilog/makefile   | 37 +++++++++++++++++++
 des/sim/verilog/tb_des.tcl | 10 +++++
 des/sim/verilog/tb_des.v   | 76 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 123 insertions(+)
 create mode 100644 des/sim/verilog/makefile
 create mode 100644 des/sim/verilog/tb_des.tcl
 create mode 100644 des/sim/verilog/tb_des.v

diff --git a/des/sim/verilog/makefile b/des/sim/verilog/makefile
new file mode 100644
index 0000000..ca33ab4
--- /dev/null
+++ b/des/sim/verilog/makefile
@@ -0,0 +1,37 @@
+# ======================================================================
+# DES encryption/decryption
+# algorithm according to FIPS 46-3 specification
+# Copyright (C) 2012 Torsten Meissner
+#-----------------------------------------------------------------------
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+# ======================================================================
+
+
+all : sim wave
+
+sim : tb_des.vcd
+
+
+tb_des.vcd : ../../rtl/verilog/*.v tb_des.v
+	iverilog -Wall -s tb_des -o tb_des tb_des.v ../../rtl/verilog/des.v
+	vvp tb_des
+
+wave : tb_des.vcd
+	gtkwave -T tb_des.tcl tb_des.vcd
+	
+clean :
+	echo "# cleaning simulation files"
+	rm -f tb_des
+	rm -f tb_des.vcd
diff --git a/des/sim/verilog/tb_des.tcl b/des/sim/verilog/tb_des.tcl
new file mode 100644
index 0000000..46bbb0e
--- /dev/null
+++ b/des/sim/verilog/tb_des.tcl
@@ -0,0 +1,10 @@
+set signals [list]
+lappend signals "tb_des.reset"
+lappend signals "tb_des.clk"
+lappend signals "tb_des.validin"
+lappend signals "tb_des.mode"
+lappend signals "tb_des.key"
+lappend signals "tb_des.datain"
+lappend signals "tb_des.validout"
+lappend signals "tb_des.dataout"
+set num_added [ gtkwave::addSignalsFromList $signals ]
diff --git a/des/sim/verilog/tb_des.v b/des/sim/verilog/tb_des.v
new file mode 100644
index 0000000..a9201e7
--- /dev/null
+++ b/des/sim/verilog/tb_des.v
@@ -0,0 +1,76 @@
+// ======================================================================
+// DES encryption/decryption testbench
+// tests according to NIST 800-17 special publication
+// Copyright (C) 2012 Torsten Meissner
+//-----------------------------------------------------------------------
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+// ======================================================================
+
+
+module tb_des;
+
+
+  initial begin
+     $dumpfile ("tb_des.vcd");
+     $dumpvars (0, tb_des);
+  end
+
+
+  reg reset = 0;
+
+  initial begin
+    #20 reset = 1;
+    #1000 $finish;
+  end
+
+  reg clk = 0;
+  always #5 clk = !clk;
+
+  reg mode;
+  reg [0:63] key;
+  reg [0:63] datain;
+  reg validin;
+
+  always @(posedge clk, reset) begin
+    if(~reset) begin
+      mode    <= 0;
+      validin <= 0;
+      key     <= 0;
+      datain  <= 0;
+    end
+    else begin
+      mode    <= 1;
+      validin <= 1;
+      key     <= key + 1;
+      datain  <= datain + 1;
+    end
+  end
+
+  wire [0:63] dataout;
+  wire validout;
+
+  des i_des (
+    .reset_i(reset),
+    .clk_i(clk),
+    .mode_i(mode),
+    .key_i(key),
+    .data_i(datain),
+    .valid_i(validin),
+    .data_o(dataout),
+    .valid_o(validout)
+  );
+
+
+endmodule