From 9a340f552421691f908f3945a719db49e6296e20 Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Fri, 22 Mar 2013 13:30:40 +0100 Subject: [PATCH] added timescale directive and set it to 1 ns/1 ps --- des/sim/verilog/tb_des.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/des/sim/verilog/tb_des.v b/des/sim/verilog/tb_des.v index 82df3ec..ac0429a 100644 --- a/des/sim/verilog/tb_des.v +++ b/des/sim/verilog/tb_des.v @@ -18,6 +18,8 @@ // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA // ====================================================================== +`timescale 1ns/1ps + module tb_des;