From a2c530928e434c360c14238e309272e756203267 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Sun, 26 Jul 2020 22:17:52 +0200 Subject: [PATCH] Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring --- aes/rtl/vhdl/aes.vhd | 67 +++++- aes/rtl/vhdl/aes_dec.vhd | 50 ++-- aes/syn/vhdl/Makefile | 49 ++++ cbcmac_aes/syn/vhdl/Makefile | 48 ++++ cbcmac_des/syn/vhdl/Makefile | 48 ++++ ctraes/rtl/vhdl/ctraes.vhd | 2 +- ctraes/syn/vhdl/Makefile | 48 ++++ des/rtl/vhdl/des_pkg.vhd | 19 ++ des/syn/vhdl/Makefile | 21 +- tdes/rtl/vhdl/des.vhd | 340 --------------------------- tdes/rtl/vhdl/des_pkg.vhd | 336 -------------------------- tdes/rtl/vhdl/tdes.vhd | 140 +++++------ tdes/sim/vhdl/{makefile => Makefile} | 34 +-- tdes/sim/vhdl/tb_tdes.vhd | 68 ++---- tdes/syn/vhdl/Makefile | 25 +- 15 files changed, 431 insertions(+), 864 deletions(-) create mode 100644 aes/syn/vhdl/Makefile create mode 100644 cbcmac_aes/syn/vhdl/Makefile create mode 100644 cbcmac_des/syn/vhdl/Makefile create mode 100644 ctraes/syn/vhdl/Makefile delete mode 100644 tdes/rtl/vhdl/des.vhd delete mode 100644 tdes/rtl/vhdl/des_pkg.vhd rename tdes/sim/vhdl/{makefile => Makefile} (71%) diff --git a/aes/rtl/vhdl/aes.vhd b/aes/rtl/vhdl/aes.vhd index 8faaac3..769b85d 100644 --- a/aes/rtl/vhdl/aes.vhd +++ b/aes/rtl/vhdl/aes.vhd @@ -1,7 +1,7 @@ -- ====================================================================== -- AES encryption/decryption -- algorithm according to FIPS 197 specification --- Copyright (C) 2011 Torsten Meissner +-- Copyright (C) 2020 Torsten Meissner ------------------------------------------------------------------------- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -34,12 +34,12 @@ entity aes is port ( reset_i : in std_logic; -- async reset clk_i : in std_logic; -- clock - mode_i : in std_logic; -- aes-modus: 0 = encrypt, 1 = decrypt - key_i : in std_logic_vector(0 TO 127); -- key input - data_i : in std_logic_vector(0 TO 127); -- data input + mode_i : in std_logic; -- mode: 0 = encrypt, 1 = decrypt + key_i : in std_logic_vector(0 to 127); -- key input + data_i : in std_logic_vector(0 to 127); -- data input valid_i : in std_logic; -- input key/data valid flag accept_o : out std_logic; - data_o : out std_logic_vector(0 TO 127); -- data output + data_o : out std_logic_vector(0 to 127); -- data output valid_o : out std_logic; -- output data valid flag accept_i : in std_logic ); @@ -50,10 +50,67 @@ end entity aes; architecture rtl of aes is + signal s_mode : std_logic; + signal s_accept_enc : std_logic; + signal s_valid_enc : std_logic; + signal s_data_enc : std_logic_vector(data_o'range); + signal s_accept_dec : std_logic; + signal s_valid_dec : std_logic; + signal s_data_dec : std_logic_vector(data_o'range); + + begin + inputregister : process (clk_i, reset_i) is + begin + if (reset_i = '0') then + s_mode <= '0'; + elsif(rising_edge(clk_i)) then + if (valid_i = '1' and accept_o = '1') then + s_mode <= mode_i; + end if; + end if; + end process inputregister; + + + accept_o <= s_accept_enc and s_accept_dec; + data_o <= s_data_enc when s_mode = '0' else s_data_dec; + valid_o <= s_valid_enc when s_mode = '0' else s_valid_dec; + + + i_aes_enc : entity work.aes_enc + generic map ( + design_type => design_type + ) + port map ( + reset_i => reset_i, + clk_i => clk_i, + key_i => key_i, + data_i => data_i, + valid_i => valid_i and not mode_i, + accept_o => s_accept_enc, + data_o => s_data_enc, + valid_o => s_valid_enc, + accept_i => accept_i + ); + i_aes_dec : entity work.aes_dec + generic map ( + design_type => design_type + ) + port map ( + reset_i => reset_i, + clk_i => clk_i, + key_i => key_i, + data_i => data_i, + valid_i => valid_i and mode_i, + accept_o => s_accept_dec, + data_o => s_data_dec, + valid_o => s_valid_dec, + accept_i => accept_i + ); + end architecture rtl; diff --git a/aes/rtl/vhdl/aes_dec.vhd b/aes/rtl/vhdl/aes_dec.vhd index 44663f6..2cd03dd 100644 --- a/aes/rtl/vhdl/aes_dec.vhd +++ b/aes/rtl/vhdl/aes_dec.vhd @@ -120,36 +120,48 @@ begin end process DeCryptP; - -- synthesis off - verification : block is + psl : block is - signal s_data : std_logic_vector(0 to 127); + signal s_key , s_din, s_dout : std_logic_vector(0 to 127) := (others => '0'); begin - s_data <= data_o when rising_edge(clk_i) else - 128x"0" when reset_i = '0'; + process (clk_i) is + begin + if (rising_edge(clk_i)) then + s_key <= key_i; + s_din <= data_i; + s_dout <= data_o; + end if; + end process; - default clock is rising_edge(Clk_i); + default clock is rising_edge(clk_i); - cover {accept_o}; - assert always (accept_o -> s_round = 0); + -- initial reset + restrict {not reset_i; reset_i[+]}[*1]; - cover {valid_i and accept_o}; - assert always (valid_i and accept_o -> next not accept_o); + -- constraints + assume always (valid_i and not accept_o -> next valid_i); + assume always (valid_i and not accept_o -> next key_i = s_key); + assume always (valid_i and not accept_o -> next data_i = s_din); - cover {valid_o}; - assert always (valid_o -> s_round = t_dec_rounds'high); + ACCEPTO_c : cover {accept_o}; + ACCEPT_IN_ROUND_0_ONLY_a : assert always (accept_o -> s_round = 0); - cover {valid_o and accept_i}; - assert always (valid_o and accept_i -> next not valid_o); + VALIDI_AND_ACCEPTO_c : cover {valid_i and accept_o}; + ACCEPT_OFF_WHEN_VALID_a : assert always (valid_i and accept_o -> next not accept_o); - cover {valid_o and not accept_i}; - assert always (valid_o and not accept_i -> next valid_o); - assert always (valid_o and not accept_i -> next data_o = s_data); + VALIDO_c : cover {valid_o}; + VALID_IN_LAST_ROUND_ONLY_a : assert always (valid_o -> s_round = t_enc_rounds'high); - end block verification; - -- synthesis on + VALIDO_AND_ACCEPTI_c : cover {valid_o and accept_i}; + VALID_OFF_WHEN_ACCEPTED_a : assert always (valid_o and accept_i -> next not valid_o); + + VALIDO_AND_NOT_ACCEPTI_c : cover {valid_o and not accept_i}; + VALID_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next valid_o); + DATA_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next data_o = s_dout); + + end block psl; end generate IterG; diff --git a/aes/syn/vhdl/Makefile b/aes/syn/vhdl/Makefile new file mode 100644 index 0000000..6116b28 --- /dev/null +++ b/aes/syn/vhdl/Makefile @@ -0,0 +1,49 @@ +# ====================================================================== +# AES encryption/decryption +# algorithm according to FIPS 197 specification +# Copyright (C) 2020 Torsten Meissner +#----------------------------------------------------------------------- +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# ====================================================================== + + +DESIGN_NAME := aes +SRC_FILES := ../../rtl/vhdl/aes_pkg.vhd \ + ../../rtl/vhdl/aes_enc.vhd \ + ../../rtl/vhdl/aes_dec.vhd \ + ../../rtl/vhdl/aes.vhd +VHD_STD := 08 + + +.PHONY: all +all : $(DESIGN_NAME)_synth.vhd syn + +.PHONY: syn +syn: $(DESIGN_NAME).json + + +$(DESIGN_NAME).o: $(SRC_FILES) + ghdl -a --std=$(VHD_STD) $(SRC_FILES) + +$(DESIGN_NAME)_synth.vhd: $(SRC_FILES) + ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@ + +$(DESIGN_NAME).json: $(DESIGN_NAME).o + yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@' + + +clean : + echo "# Cleaning files" + rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd diff --git a/cbcmac_aes/syn/vhdl/Makefile b/cbcmac_aes/syn/vhdl/Makefile new file mode 100644 index 0000000..09e7a4a --- /dev/null +++ b/cbcmac_aes/syn/vhdl/Makefile @@ -0,0 +1,48 @@ +# ====================================================================== +# AES encryption/decryption +# algorithm according to FIPS 197 specification +# Copyright (C) 2020 Torsten Meissner +#----------------------------------------------------------------------- +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# ====================================================================== + + +DESIGN_NAME := cbcmac_aes +SRC_FILES := ../../../aes/rtl/vhdl/aes_pkg.vhd \ + ../../../aes/rtl/vhdl/aes_enc.vhd \ + ../../rtl/vhdl/$(DESIGN_NAME).vhd +VHD_STD := 08 + + +.PHONY: all +all : $(DESIGN_NAME)_synth.vhd syn + +.PHONY: syn +syn: $(DESIGN_NAME).json + + +$(DESIGN_NAME).o: $(SRC_FILES) + ghdl -a --std=$(VHD_STD) $(SRC_FILES) + +$(DESIGN_NAME)_synth.vhd: $(SRC_FILES) + ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@ + +$(DESIGN_NAME).json: $(DESIGN_NAME).o + yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@' + + +clean : + echo "# Cleaning files" + rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd diff --git a/cbcmac_des/syn/vhdl/Makefile b/cbcmac_des/syn/vhdl/Makefile new file mode 100644 index 0000000..37446c9 --- /dev/null +++ b/cbcmac_des/syn/vhdl/Makefile @@ -0,0 +1,48 @@ +# ====================================================================== +# CBCMAC-DES encryption/decryption +# algorithm according to FIPS 46-3 specification +# Copyright (C) 2020 Torsten Meissner +#----------------------------------------------------------------------- +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# ====================================================================== + + +DESIGN_NAME := cbcmac_des +DES_SRC_FILES := ../../../des/rtl/vhdl/des_pkg.vhd ../../../des/rtl/vhdl/des.vhd +DESIGN_SRC_FILES := ../../rtl/vhdl/$(DESIGN_NAME).vhd +SRC_FILES := $(DES_SRC_FILES) $(DESIGN_SRC_FILES) +VHD_STD := 08 + + +.PHONY: all +all : $(DESIGN_NAME)_synth.vhd syn + +.PHONY: syn +syn: $(DESIGN_NAME).json + + +$(DESIGN_NAME).o: $(SRC_FILES) + ghdl -a --std=$(VHD_STD) $(SRC_FILES) + +$(DESIGN_NAME)_synth.vhd: $(SRC_FILES) + ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@ + +$(DESIGN_NAME).json: $(DESIGN_NAME).o + yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@' + + +clean : + echo "# Cleaning files" + rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd diff --git a/ctraes/rtl/vhdl/ctraes.vhd b/ctraes/rtl/vhdl/ctraes.vhd index 106f794..cfc8b71 100644 --- a/ctraes/rtl/vhdl/ctraes.vhd +++ b/ctraes/rtl/vhdl/ctraes.vhd @@ -101,7 +101,7 @@ begin end process counterreg; - i_aes : aes_enc + i_aes_enc : entity work.aes_enc generic map ( design_type => "ITER" ) diff --git a/ctraes/syn/vhdl/Makefile b/ctraes/syn/vhdl/Makefile new file mode 100644 index 0000000..65bb701 --- /dev/null +++ b/ctraes/syn/vhdl/Makefile @@ -0,0 +1,48 @@ +# ====================================================================== +# AES encryption/decryption +# algorithm according to FIPS 197 specification +# Copyright (C) 2020 Torsten Meissner +#----------------------------------------------------------------------- +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# ====================================================================== + + +DESIGN_NAME := ctraes +SRC_FILES := ../../../aes/rtl/vhdl/aes_pkg.vhd \ + ../../../aes/rtl/vhdl/aes_enc.vhd \ + ../../rtl/vhdl/$(DESIGN_NAME).vhd +VHD_STD := 08 + + +.PHONY: all +all : $(DESIGN_NAME)_synth.vhd syn + +.PHONY: syn +syn: $(DESIGN_NAME).json + + +$(DESIGN_NAME).o: $(SRC_FILES) + ghdl -a --std=$(VHD_STD) $(SRC_FILES) + +$(DESIGN_NAME)_synth.vhd: $(SRC_FILES) + ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@ + +$(DESIGN_NAME).json: $(DESIGN_NAME).o + yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@' + + +clean : + echo "# Cleaning files" + rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd diff --git a/des/rtl/vhdl/des_pkg.vhd b/des/rtl/vhdl/des_pkg.vhd index 5b3cef5..18cfff2 100644 --- a/des/rtl/vhdl/des_pkg.vhd +++ b/des/rtl/vhdl/des_pkg.vhd @@ -29,6 +29,25 @@ library ieee; package des_pkg is + component des is + generic ( + design_type : string := "ITER" + ); + port ( + reset_i : in std_logic; -- async reset + clk_i : in std_logic; -- clock + mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt + key_i : in std_logic_vector(0 to 63); -- key input + data_i : in std_logic_vector(0 to 63); -- data input + valid_i : in std_logic; -- input key/data valid + accept_o : out std_logic; -- input accept + data_o : out std_logic_vector(0 to 63); -- data output + valid_o : out std_logic; -- output data valid flag + accept_i : in std_logic -- output accept + ); + end component des; + + type ip_matrix is array (0 to 63) of natural range 0 to 63; constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17, 9, 1, 59, 51, 43, 35, 27, 19, 11, 3, diff --git a/des/syn/vhdl/Makefile b/des/syn/vhdl/Makefile index beb23d9..ae08aea 100644 --- a/des/syn/vhdl/Makefile +++ b/des/syn/vhdl/Makefile @@ -19,27 +19,28 @@ # ====================================================================== -SRC_FILES := ../../rtl/vhdl/des_pkg.vhd ../../rtl/vhdl/des.vhd -VHD_STD := 08 +DESIGN_NAME := des +SRC_FILES := ../../../des/rtl/vhdl/$(DESIGN_NAME)_pkg.vhd ../../../des/rtl/vhdl/$(DESIGN_NAME).vhd +VHD_STD := 08 .PHONY: all -all: des_synth.vhd syn +all : $(DESIGN_NAME)_synth.vhd syn .PHONY: syn -syn: des.json +syn: $(DESIGN_NAME).json -des.o: $(SRC_FILES) +$(DESIGN_NAME).o: $(SRC_FILES) ghdl -a --std=$(VHD_STD) $(SRC_FILES) -des_synth.vhd: $(SRC_FILES) - ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e des > $@ +$(DESIGN_NAME)_synth.vhd: $(SRC_FILES) + ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@ -des.json: des.o - yosys -m ghdl -p 'ghdl --std=08 --no-formal des; synth_ice40 -json $@' +$(DESIGN_NAME).json: $(DESIGN_NAME).o + yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@' clean : echo "# Cleaning files" - rm -f *.o work*.cf des.json des_synth.vhd + rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd diff --git a/tdes/rtl/vhdl/des.vhd b/tdes/rtl/vhdl/des.vhd deleted file mode 100644 index 9ebc905..0000000 --- a/tdes/rtl/vhdl/des.vhd +++ /dev/null @@ -1,340 +0,0 @@ --- ====================================================================== --- DES encryption/decryption --- algorithm according to FIPS 46-3 specification --- Copyright (C) 2007 Torsten Meissner -------------------------------------------------------------------------- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. - --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. - --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA --- ====================================================================== - - --- Revision 1.0 2007/02/04 --- Initial release --- Revision 1.1 2007/02/05 --- Corrected error in use of mode register for key calculation - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.numeric_std.ALL; -USE work.des_pkg.ALL; - - -ENTITY des IS - PORT ( - reset_i : in std_logic; -- async reset - clk_i : IN std_logic; -- clock - mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt - key_i : IN std_logic_vector(0 TO 63); -- key input - data_i : IN std_logic_vector(0 TO 63); -- data input - valid_i : IN std_logic; -- input key/data valid flag - data_o : OUT std_logic_vector(0 TO 63); -- data output - valid_o : OUT std_logic -- output data valid flag - ); -END ENTITY des; - - -ARCHITECTURE rtl OF des IS - -BEGIN - - crypt : PROCESS ( clk_i ) IS - -- variables for key calculation - VARIABLE c0 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c1 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c2 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c3 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c4 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c5 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c6 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c7 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c8 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c9 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d0 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d1 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d2 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d3 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d4 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d5 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d6 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d7 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d8 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d9 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0'); - VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0'); - -- key variables - VARIABLE key1 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key2 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key3 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key4 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key5 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key6 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key7 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key8 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key9 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0'); - VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0'); - -- variables for left & right data blocks - VARIABLE l0 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l1 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l2 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l3 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l4 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l5 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l6 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l7 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l8 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l9 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r0 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r1 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r2 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r3 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r4 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r5 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r6 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r7 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r8 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r9 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0'); - VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0'); - -- variables for mode & valid shift registers - VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0'); - VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0'); - BEGIN - if(reset_i = '0') then - data_o <= (others => '0'); - valid_o <= '0'; - elsif rising_edge( clk_i ) THEN - -- shift registers - valid(1 TO 17) := valid(0 TO 16); - valid(0) := valid_i; - mode(1 TO 16) := mode(0 TO 15); - mode(0) := mode_i; - -- output stage - valid_o <= valid(17); - data_o <= ipn( ( r16 & l16 ) ); - -- 16. stage - IF mode(16) = '0' THEN - c16 := c15(1 TO 27) & c15(0); - d16 := d15(1 TO 27) & d15(0); - ELSE - c16 := c15(27) & c15(0 TO 26); - d16 := d15(27) & d15(0 TO 26); - END IF; - key16 := pc2( ( c16 & d16 ) ); - l16 := r15; - r16 := l15 xor ( f( r15, key16 ) ); - -- 15. stage - IF mode(15) = '0' THEN - c15 := c14(2 TO 27) & c14(0 TO 1); - d15 := d14(2 TO 27) & d14(0 TO 1); - ELSE - c15 := c14(26 TO 27) & c14(0 TO 25); - d15 := d14(26 TO 27) & d14(0 TO 25); - END IF; - key15 := pc2( ( c15 & d15 ) ); - l15 := r14; - r15 := l14 xor ( f( r14, key15 ) ); - -- 14. stage - IF mode(14) = '0' THEN - c14 := c13(2 TO 27) & c13(0 TO 1); - d14 := d13(2 TO 27) & d13(0 TO 1); - ELSE - c14 := c13(26 TO 27) & c13(0 TO 25); - d14 := d13(26 TO 27) & d13(0 TO 25); - END IF; - key14 := pc2( ( c14 & d14 ) ); - l14 := r13; - r14 := l13 xor ( f( r13, key14 ) ); - -- 13. stage - IF mode(13) = '0' THEN - c13 := c12(2 TO 27) & c12(0 TO 1); - d13 := d12(2 TO 27) & d12(0 TO 1); - ELSE - c13 := c12(26 TO 27) & c12(0 TO 25); - d13 := d12(26 TO 27) & d12(0 TO 25); - END IF; - key13 := pc2( ( c13 & d13 ) ); - l13 := r12; - r13 := l12 xor ( f( r12, key13 ) ); - -- 12. stage - IF mode(12) = '0' THEN - c12 := c11(2 TO 27) & c11(0 TO 1); - d12 := d11(2 TO 27) & d11(0 TO 1); - ELSE - c12 := c11(26 TO 27) & c11(0 TO 25); - d12 := d11(26 TO 27) & d11(0 TO 25); - END IF; - key12 := pc2( ( c12 & d12 ) ); - l12 := r11; - r12 := l11 xor ( f( r11, key12 ) ); - -- 11. stage - IF mode(11) = '0' THEN - c11 := c10(2 TO 27) & c10(0 TO 1); - d11 := d10(2 TO 27) & d10(0 TO 1); - ELSE - c11 := c10(26 TO 27) & c10(0 TO 25); - d11 := d10(26 TO 27) & d10(0 TO 25); - END IF; - key11 := pc2( ( c11 & d11 ) ); - l11 := r10; - r11 := l10 xor ( f( r10, key11 ) ); - -- 10. stage - IF mode(10) = '0' THEN - c10 := c9(2 TO 27) & c9(0 TO 1); - d10 := d9(2 TO 27) & d9(0 TO 1); - ELSE - c10 := c9(26 TO 27) & c9(0 TO 25); - d10 := d9(26 TO 27) & d9(0 TO 25); - END IF; - key10 := pc2( ( c10 & d10 ) ); - l10 := r9; - r10 := l9 xor ( f( r9, key10 ) ); - -- 9. stage - IF mode(9) = '0' THEN - c9 := c8(1 TO 27) & c8(0); - d9 := d8(1 TO 27) & d8(0); - ELSE - c9 := c8(27) & c8(0 TO 26); - d9 := d8(27) & d8(0 TO 26); - END IF; - key9 := pc2( ( c9 & d9 ) ); - l9 := r8; - r9 := l8 xor ( f( r8, key9 ) ); - -- 8. stage - IF mode(8) = '0' THEN - c8 := c7(2 TO 27) & c7(0 TO 1); - d8 := d7(2 TO 27) & d7(0 TO 1); - ELSE - c8 := c7(26 TO 27) & c7(0 TO 25); - d8 := d7(26 TO 27) & d7(0 TO 25); - END IF; - key8 := pc2( ( c8 & d8 ) ); - l8 := r7; - r8 := l7 xor ( f( r7, key8 ) ); - -- 7. stage - IF mode(7) = '0' THEN - c7 := c6(2 TO 27) & c6(0 TO 1); - d7 := d6(2 TO 27) & d6(0 TO 1); - ELSE - c7 := c6(26 TO 27) & c6(0 TO 25); - d7 := d6(26 TO 27) & d6(0 TO 25); - END IF; - key7 := pc2( ( c7 & d7 ) ); - l7 := r6; - r7 := l6 xor ( f( r6, key7 ) ); - -- 6. stage - IF mode(6) = '0' THEN - c6 := c5(2 TO 27) & c5(0 TO 1); - d6 := d5(2 TO 27) & d5(0 TO 1); - ELSE - c6 := c5(26 TO 27) & c5(0 TO 25); - d6 := d5(26 TO 27) & d5(0 TO 25); - END IF; - key6 := pc2( ( c6 & d6 ) ); - l6 := r5; - r6 := l5 xor ( f( r5, key6 ) ); - -- 5. stage - IF mode(5) = '0' THEN - c5 := c4(2 TO 27) & c4(0 TO 1); - d5 := d4(2 TO 27) & d4(0 TO 1); - ELSE - c5 := c4(26 TO 27) & c4(0 TO 25); - d5 := d4(26 TO 27) & d4(0 TO 25); - END IF; - key5 := pc2( ( c5 & d5 ) ); - l5 := r4; - r5 := l4 xor ( f( r4, key5 ) ); - -- 4. stage - IF mode(4) = '0' THEN - c4 := c3(2 TO 27) & c3(0 TO 1); - d4 := d3(2 TO 27) & d3(0 TO 1); - ELSE - c4 := c3(26 TO 27) & c3(0 TO 25); - d4 := d3(26 TO 27) & d3(0 TO 25); - END IF; - key4 := pc2( ( c4 & d4 ) ); - l4 := r3; - r4 := l3 xor ( f( r3, key4 ) ); - -- 3. stage - IF mode(3) = '0' THEN - c3 := c2(2 TO 27) & c2(0 TO 1); - d3 := d2(2 TO 27) & d2(0 TO 1); - ELSE - c3 := c2(26 TO 27) & c2(0 TO 25); - d3 := d2(26 TO 27) & d2(0 TO 25); - END IF; - key3 := pc2( ( c3 & d3 ) ); - l3 := r2; - r3 := l2 xor ( f( r2, key3 ) ); - -- 2. stage - IF mode(2) = '0' THEN - c2 := c1(1 TO 27) & c1(0); - d2 := d1(1 TO 27) & d1(0); - ELSE - c2 := c1(27) & c1(0 TO 26); - d2 := d1(27) & d1(0 TO 26); - END IF; - key2 := pc2( ( c2 & d2 ) ); - l2 := r1; - r2 := l1 xor ( f( r1, key2 ) ); - -- 1. stage - IF mode(1) = '0' THEN - c1 := c0(1 TO 27) & c0(0); - d1 := d0(1 TO 27) & d0(0); - ELSE - c1 := c0; - d1 := d0; - END IF; - key1 := pc2( ( c1 & d1 ) ); - l1 := r0; - r1 := l0 xor ( f( r0, key1 ) ); - -- input stage - l0 := ip( data_i )(0 TO 31); - r0 := ip( data_i )(32 TO 63); - c0 := pc1_c( key_i ); - d0 := pc1_d( key_i ); - END IF; - END PROCESS crypt; - -END ARCHITECTURE rtl; diff --git a/tdes/rtl/vhdl/des_pkg.vhd b/tdes/rtl/vhdl/des_pkg.vhd deleted file mode 100644 index 220704e..0000000 --- a/tdes/rtl/vhdl/des_pkg.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- ====================================================================== --- DES encryption/decryption --- package file with functions --- Copyright (C) 2007 Torsten Meissner -------------------------------------------------------------------------- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. - --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. - --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA --- ====================================================================== - - --- Revision 1.0 2007/02/04 --- Initial release - - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.numeric_std.ALL; - - - -PACKAGE des_pkg IS - - - FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - - FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; - FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector; - - FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector; - - FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector; - - FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector; - FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector; - - TYPE ip_matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63; - constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17, 9, 1, - 59, 51, 43, 35, 27, 19, 11, 3, - 61, 53, 45, 37, 29, 21, 13, 5, - 63, 55, 47, 39, 31, 23, 15, 7, - 56, 48, 40, 32, 24, 16, 8, 0, - 58, 50, 42, 34, 26, 18, 10, 2, - 60, 52, 44, 36, 28, 20, 12, 4, - 62, 54, 46, 38, 30, 22, 14, 6); - constant ipn_table : ip_matrix := (39, 7, 47, 15, 55, 23, 63, 31, - 38, 6, 46, 14, 54, 22, 62, 30, - 37, 5, 45, 13, 53, 21, 61, 29, - 36, 4, 44, 12, 52, 20, 60, 28, - 35, 3, 43, 11, 51, 19, 59, 27, - 34, 2, 42, 10, 50, 18, 58, 26, - 33, 1, 41, 9, 49, 17, 57, 25, - 32, 0, 40, 8, 48, 16, 56, 24); - - TYPE e_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31; - constant e_table : e_matrix := (31, 0, 1, 2, 3, 4, - 3, 4, 5, 6, 7, 8, - 7, 8, 9, 10, 11, 12, - 11, 12, 13, 14, 15, 16, - 15, 16, 17, 18, 19, 20, - 19, 20, 21, 22, 23, 24, - 23, 24, 25, 26, 27, 28, - 27, 28, 29, 30, 31, 0); - - TYPE s_matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15; - constant s1_table : s_matrix := (0 => (14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7), - 1 => ( 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8), - 2 => ( 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0), - 3 => (15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13)); - constant s2_table : s_matrix := (0 => (15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10), - 1 => ( 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5), - 2 => ( 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15), - 3 => (13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9)); - constant s3_table : s_matrix := (0 => (10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8), - 1 => (13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1), - 2 => (13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7), - 3 => ( 1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12)); - constant s4_table : s_matrix := (0 => ( 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15), - 1 => (13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9), - 2 => (10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4), - 3 => ( 3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14)); - constant s5_table : s_matrix := (0 => ( 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9), - 1 => (14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6), - 2 => ( 4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14), - 3 => (11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3)); - constant s6_table : s_matrix := (0 => (12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11), - 1 => (10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8), - 2 => ( 9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6), - 3 => ( 4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13)); - constant s7_table : s_matrix := (0 => ( 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1), - 1 => (13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6), - 2 => ( 1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2), - 3 => ( 6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12)); - constant s8_table : s_matrix := (0 => (13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7), - 1 => ( 1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2), - 2 => ( 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8), - 3 => ( 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11)); - - type pc_matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63; - constant pc1c_table : pc_matrix := (56, 48, 40, 32, 24, 16, 8, - 0, 57, 49, 41, 33, 25, 17, - 9, 1, 58, 50, 42, 34, 26, - 18, 10, 2, 59, 51, 43, 35); - constant pc1d_table : pc_matrix := (62, 54, 46, 38, 30, 22, 14, - 6, 61, 53, 45, 37, 29, 21, - 13, 5, 60, 52, 44, 36, 28, - 20, 12, 4, 27, 19, 11, 3); - - type p_matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31; - constant p_table : p_matrix := (15, 6, 19, 20, - 28, 11, 27, 16, - 0, 14, 22, 25, - 4, 17, 30, 9, - 1, 7, 23, 13, - 31, 26, 2, 8, - 18, 12, 29, 5, - 21, 10, 3, 24); - - type pc2_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63; - constant pc2_table : pc2_matrix := (13, 16, 10, 23, 0, 4, - 2, 27, 14, 5, 20, 9, - 22, 18, 11, 3, 25, 7, - 15, 6, 26, 19, 12, 1, - 40, 51, 30, 36, 46, 54, - 29, 39, 50, 44, 32, 47, - 43, 48, 38, 55, 33, 52, - 45, 41, 49, 35, 28, 31); - - -END PACKAGE des_pkg; - - - -PACKAGE BODY des_pkg IS - - - FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 63); - BEGIN - FOR index IN 0 TO 63 LOOP - result( index ) := input_vector( ip_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION ip; - - FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 63); - BEGIN - FOR index IN 0 TO 63 LOOP - result( index ) := input_vector( ipn_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION ipn; - - FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 47); - BEGIN - FOR index IN 0 TO 47 LOOP - result( index ) := input_vector( e_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION e; - - FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s1_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s1; - - FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s2_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s2; - - FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s3_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s3; - - FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s4_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s4; - - FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s5_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s5; - - FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s6_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s6; - - FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s7_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s7; - - FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS - VARIABLE int : std_logic_vector(0 TO 1); - VARIABLE i : integer RANGE 0 TO 3; - VARIABLE j : integer RANGE 0 TO 15; - VARIABLE result : std_logic_vector(0 TO 3); - BEGIN - int := input_vector( 0 ) & input_vector( 5 ); - i := to_integer( unsigned( int ) ); - j := to_integer( unsigned( input_vector( 1 TO 4) ) ); - result := std_logic_vector( to_unsigned( s8_table( i, j ), 4 ) ); - RETURN result; - END FUNCTION s8; - - FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 31); - BEGIN - FOR index IN 0 TO 31 LOOP - result( index ) := input_vector( p_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION p; - - FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS - VARIABLE intern : std_logic_vector(0 TO 47); - VARIABLE result : std_logic_vector(0 TO 31); - BEGIN - intern := e( input_r ) xor input_key; - result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) & - s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) ); - RETURN result; - END FUNCTION f; - - FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 27); - BEGIN - FOR index IN 0 TO 27 LOOP - result( index ) := input_vector( pc1c_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc1_c; - - FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS - - VARIABLE result : std_logic_vector(0 TO 27); - BEGIN - FOR index IN 0 TO 27 LOOP - result( index ) := input_vector( pc1d_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc1_d; - - FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(0 TO 47); - BEGIN - FOR index IN 0 TO 47 LOOP - result( index ) := input_vector( pc2_table( index ) ); - END LOOP; - RETURN result; - END FUNCTION pc2; - - -END PACKAGE BODY des_pkg; diff --git a/tdes/rtl/vhdl/tdes.vhd b/tdes/rtl/vhdl/tdes.vhd index 61405ad..81fa35b 100644 --- a/tdes/rtl/vhdl/tdes.vhd +++ b/tdes/rtl/vhdl/tdes.vhd @@ -19,29 +19,28 @@ -- ====================================================================== --- Revision 0.1 2011/10/08 --- Initial release - - library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; + use work.des_pkg.all; + entity tdes is port ( reset_i : in std_logic; -- async reset clk_i : in std_logic; -- clock mode_i : in std_logic; -- tdes-modus: 0 = encrypt, 1 = decrypt - key1_i : in std_logic_vector(0 TO 63); -- key input - key2_i : in std_logic_vector(0 TO 63); -- key input - key3_i : in std_logic_vector(0 TO 63); -- key input - data_i : in std_logic_vector(0 TO 63); -- data input + key1_i : in std_logic_vector(0 to 63); -- key input + key2_i : in std_logic_vector(0 to 63); -- key input + key3_i : in std_logic_vector(0 to 63); -- key input + data_i : in std_logic_vector(0 to 63); -- data input valid_i : in std_logic; -- input key/data valid flag - data_o : out std_logic_vector(0 TO 63); -- data output + accept_o : out std_logic; + data_o : out std_logic_vector(0 to 63); -- data output valid_o : out std_logic; -- output data valid flag - ready_o : out std_logic + accept_i : in std_logic ); end entity tdes; @@ -49,56 +48,36 @@ end entity tdes; architecture rtl of tdes is - component des is - port ( - reset_i : in std_logic; - clk_i : IN std_logic; -- clock - mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt - key_i : IN std_logic_vector(0 TO 63); -- key input - data_i : IN std_logic_vector(0 TO 63); -- data input - valid_i : IN std_logic; -- input key/data valid flag - data_o : OUT std_logic_vector(0 TO 63); -- data output - valid_o : OUT std_logic -- output data valid flag - ); - end component des; - - - signal s_ready : std_logic; - signal s_mode : std_logic; - signal s_des2_mode : std_logic; - signal s_des1_validin : std_logic := '0'; - signal s_des1_validout : std_logic; - signal s_des2_validout : std_logic; - signal s_des3_validout : std_logic; - signal s_key1 : std_logic_vector(0 to 63); - signal s_key2 : std_logic_vector(0 to 63); - signal s_key3 : std_logic_vector(0 to 63); - signal s_des1_key : std_logic_vector(0 to 63); - signal s_des3_key : std_logic_vector(0 to 63); - signal s_des1_dataout : std_logic_vector(0 to 63); - signal s_des2_dataout : std_logic_vector(0 to 63); + signal s_mode : std_logic; + signal s_des1_validout : std_logic; + signal s_des2_validout : std_logic; + signal s_des2_acceptout : std_logic; + signal s_des3_acceptout : std_logic; + signal s_key1 : std_logic_vector(0 to 63); + signal s_key2 : std_logic_vector(0 to 63); + signal s_key3 : std_logic_vector(0 to 63); + signal s_des1_key : std_logic_vector(0 to 63); + signal s_des3_key : std_logic_vector(0 to 63); + signal s_des1_dataout : std_logic_vector(0 to 63); + signal s_des2_dataout : std_logic_vector(0 to 63); -begin +begin - ready_o <= s_ready; - valid_o <= s_des3_validout; - s_des2_mode <= not(s_mode); - s_des1_validin <= valid_i and s_ready; s_des1_key <= key1_i when mode_i = '0' else key3_i; s_des3_key <= s_key3 when s_mode = '0' else s_key1; - inputregister : process(clk_i, reset_i) is + inputregister : process (clk_i, reset_i) is begin - if(reset_i = '0') then + if (reset_i = '0') then s_mode <= '0'; s_key1 <= (others => '0'); s_key2 <= (others => '0'); s_key3 <= (others => '0'); elsif(rising_edge(clk_i)) then - if(valid_i = '1' and s_ready = '1') then + if (valid_i = '1' and accept_o = '1') then s_mode <= mode_i; s_key1 <= key1_i; s_key2 <= key2_i; @@ -108,57 +87,48 @@ begin end process inputregister; - outputregister : process(clk_i, reset_i) is - begin - if(reset_i = '0') then - s_ready <= '1'; - elsif(rising_edge(clk_i)) then - if(valid_i = '1' and s_ready = '1') then - s_ready <= '0'; - end if; - if(s_des3_validout = '1') then - s_ready <= '1'; - end if; - end if; - end process outputregister; - - i1_des : des port map ( - reset_i => reset_i, - clk_i => clk_i, - mode_i => mode_i, - key_i => s_des1_key, - data_i => data_i, - valid_i => s_des1_validin, - data_o => s_des1_dataout, - valid_o => s_des1_validout + reset_i => reset_i, + clk_i => clk_i, + mode_i => mode_i, + key_i => s_des1_key, + data_i => data_i, + valid_i => valid_i, + accept_o => accept_o, + data_o => s_des1_dataout, + valid_o => s_des1_validout, + accept_i => s_des2_acceptout ); i2_des : des port map ( - reset_i => reset_i, - clk_i => clk_i, - mode_i => s_des2_mode, - key_i => s_key2, - data_i => s_des1_dataout, - valid_i => s_des1_validout, - data_o => s_des2_dataout, - valid_o => s_des2_validout + reset_i => reset_i, + clk_i => clk_i, + mode_i => not s_mode, + key_i => s_key2, + data_i => s_des1_dataout, + valid_i => s_des1_validout, + accept_o => s_des2_acceptout, + data_o => s_des2_dataout, + valid_o => s_des2_validout, + accept_i => s_des3_acceptout ); i3_des : des port map ( - reset_i => reset_i, - clk_i => clk_i, - mode_i => s_mode, - key_i => s_des3_key, - data_i => s_des2_dataout, - valid_i => s_des2_validout, - data_o => data_o, - valid_o => s_des3_validout + reset_i => reset_i, + clk_i => clk_i, + mode_i => s_mode, + key_i => s_des3_key, + data_i => s_des2_dataout, + valid_i => s_des2_validout, + accept_o => s_des3_acceptout, + data_o => data_o, + valid_o => valid_o, + accept_i => accept_i ); diff --git a/tdes/sim/vhdl/makefile b/tdes/sim/vhdl/Makefile similarity index 71% rename from tdes/sim/vhdl/makefile rename to tdes/sim/vhdl/Makefile index 6ec2d9a..8ff4f2e 100644 --- a/tdes/sim/vhdl/makefile +++ b/tdes/sim/vhdl/Makefile @@ -1,5 +1,5 @@ # ====================================================================== -# DES encryption/decryption +# TDES encryption/decryption # algorithm according to FIPS 46-3 specification # Copyright (C) 2011 Torsten Meissner #----------------------------------------------------------------------- @@ -19,24 +19,30 @@ # ====================================================================== -SRC_FILES = ../../rtl/vhdl/des_pkg.vhd ../../rtl/vhdl/des.vhd ../../rtl/vhdl/tdes.vhd +DES_SRC_FILES := ../../../des/rtl/vhdl/des_pkg.vhd ../../../des/rtl/vhdl/des.vhd +TDES_SRC_FILES := ../../rtl/vhdl/tdes.vhd +SRC_FILES := $(DES_SRC_FILES) $(TDES_SRC_FILES) +VHD_STD := 08 -all : sim wave - +.PHONY: sim sim : tb_tdes.ghw -tb_tdes.ghw : $(SRC_FILES) tb_tdes.vhd - ghdl -a $(SRC_FILES) tb_tdes.vhd - ghdl -e tb_tdes +.PHONY: all +all : wave + + +tb_des.o: $(SRC_FILES) tb_tdes.vhd + ghdl -a --std=$(VHD_STD) $(SRC_FILES) tb_tdes.vhd + +tb_tdes.ghw : tb_des.o + ghdl -e --std=$(VHD_STD) tb_tdes ghdl -r tb_tdes --wave=tb_tdes.ghw --assert-level=error --stop-time=45us - + wave : tb_tdes.ghw gtkwave -s tb_tdes.tcl tb_tdes.ghw - + + clean : - echo "# cleaning simulation files" - rm -f *.ghw - rm -f *.o - rm -f tb_tdes - rm -f work*.cf + echo "# Cleaning files" + rm -f *.ghw *.o tb_tdes work*.cf diff --git a/tdes/sim/vhdl/tb_tdes.vhd b/tdes/sim/vhdl/tb_tdes.vhd index 9ae3226..6eeae92 100644 --- a/tdes/sim/vhdl/tb_tdes.vhd +++ b/tdes/sim/vhdl/tb_tdes.vhd @@ -19,15 +19,12 @@ -- ====================================================================== --- Revision 0.1 2011/10/08 --- Initial release - - library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; + entity tb_tdes is end entity tb_tdes; @@ -56,26 +53,11 @@ architecture rtl of tb_tdes is signal s_key3 : std_logic_vector(0 to 63) := (others => '0'); signal s_datain : std_logic_vector(0 to 63) := (others => '0'); signal s_validin : std_logic := '0'; - signal s_ready : std_logic := '0'; - signal s_dataout : std_logic_vector(0 to 63); - signal s_validout : std_logic := '0'; - - - component tdes is - port ( - reset_i : in std_logic; - clk_i : in std_logic; - mode_i : in std_logic; - key1_i : in std_logic_vector(0 to 63); - key2_i : in std_logic_vector(0 TO 63); - key3_i : in std_logic_vector(0 TO 63); - data_i : in std_logic_vector(0 TO 63); - valid_i : in std_logic; - data_o : out std_logic_vector(0 TO 63); - valid_o : out std_logic; - ready_o : out std_logic - ); - end component tdes; + signal s_acceptin : std_logic; + + signal s_dataout : std_logic_vector(0 to 63); + signal s_validout : std_logic := '0'; + signal s_acceptout : std_logic := '0'; begin @@ -87,23 +69,23 @@ begin teststimuliP : process is begin - s_mode <= '0'; - s_validin <= '0'; - s_key1 <= (others => '0'); - s_key2 <= (others => '0'); - s_key3 <= (others => '0'); - s_datain <= (others => '0'); + s_mode <= '0'; + s_validin <= '0'; + s_key1 <= (others => '0'); + s_key2 <= (others => '0'); + s_key3 <= (others => '0'); + s_datain <= (others => '0'); wait until s_reset = '1'; -- ENCRYPTION TESTS -- cbc known answers test for index in c_table_test_plain'range loop - wait until rising_edge(s_clk) and s_ready = '1'; + wait until rising_edge(s_clk); s_key1 <= x"1111111111111111"; s_key2 <= x"5555555555555555"; s_key3 <= x"9999999999999999"; s_validin <= '1'; s_datain <= c_table_test_plain(index); - wait until rising_edge(s_clk); + wait until s_acceptin = '1' and rising_edge(s_clk); s_validin <= '0'; end loop; wait until rising_edge(s_clk); @@ -117,30 +99,31 @@ begin -- DECRYPTION TESTS -- cbc known answer test for index in c_table_test_plain'range loop - wait until rising_edge(s_clk) and s_ready = '1'; + wait until rising_edge(s_clk); s_key1 <= x"1111111111111111"; s_key2 <= x"5555555555555555"; s_key3 <= x"9999999999999999"; s_mode <= '1'; s_validin <= '1'; s_datain <= s_tdes_answers(index); - wait until rising_edge(s_clk); + wait until s_acceptin = '1' and rising_edge(s_clk); s_validin <= '0'; s_mode <= '0'; end loop; wait until rising_edge(s_clk); - s_mode <= '0'; - s_validin <= '0'; - s_key1 <= (others => '0'); - s_key2 <= (others => '0'); - s_key3 <= (others => '0'); - s_datain <= (others => '0'); + s_mode <= '0'; + s_validin <= '0'; + s_key1 <= (others => '0'); + s_key2 <= (others => '0'); + s_key3 <= (others => '0'); + s_datain <= (others => '0'); wait; end process teststimuliP; testcheckerP : process is begin + s_acceptout <= '1'; report "# ENCRYPTION TESTS"; for index in c_table_test_plain'range loop wait until rising_edge(s_clk) and s_validout = '1'; @@ -159,7 +142,7 @@ begin end process testcheckerP; - i_tdes : tdes + i_tdes : entity work.tdes port map ( reset_i => s_reset, clk_i => s_clk, @@ -169,9 +152,10 @@ begin key3_i => s_key3, data_i => s_datain, valid_i => s_validin, + accept_o => s_acceptin, data_o => s_dataout, valid_o => s_validout, - ready_o => s_ready + accept_i => s_acceptout ); diff --git a/tdes/syn/vhdl/Makefile b/tdes/syn/vhdl/Makefile index 2dfc68b..b53a2df 100644 --- a/tdes/syn/vhdl/Makefile +++ b/tdes/syn/vhdl/Makefile @@ -19,29 +19,30 @@ # ====================================================================== -DES_SRC_FILES := ../../../des/rtl/vhdl/des_pkg.vhd ../../../des/rtl/vhdl/des.vhd -TDES_SRC_FILES := ../../rtl/vhdl/tdes.vhd -SRC_FILES := $(DES_SRC_FILES) $(TDES_SRC_FILES) -VHD_STD := 08 +DESIGN_NAME := tdes +DES_SRC_FILES := ../../../des/rtl/vhdl/des_pkg.vhd ../../../des/rtl/vhdl/des.vhd +DESIGN_SRC_FILES := ../../rtl/vhdl/$(DESIGN_NAME).vhd +SRC_FILES := $(DES_SRC_FILES) $(DESIGN_SRC_FILES) +VHD_STD := 08 .PHONY: all -all : tdes_synth.vhd syn +all : $(DESIGN_NAME)_synth.vhd syn .PHONY: syn -syn: tdes.json +syn: $(DESIGN_NAME).json -tdes.o: $(SRC_FILES) +$(DESIGN_NAME).o: $(SRC_FILES) ghdl -a --std=$(VHD_STD) $(SRC_FILES) -tdes_synth.vhd: $(SRC_FILES) - ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e tdes > $@ +$(DESIGN_NAME)_synth.vhd: $(SRC_FILES) + ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@ -tdes.json: tdes.o - yosys -m ghdl -p 'ghdl --std=08 --no-formal tdes; synth_ice40 -json $@' +$(DESIGN_NAME).json: $(DESIGN_NAME).o + yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@' clean : echo "# Cleaning files" - rm -f *.o work*.cf tdes.json tdes_synth.vhd + rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd