From bd2f3134311f03f0fa2f756249936a27dc5fa74d Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Fri, 22 Mar 2013 13:30:05 +0100 Subject: [PATCH 1/3] removed 'outdex' reg from waveform viewer --- des/sim/verilog/tb_des.tcl | 1 - 1 file changed, 1 deletion(-) diff --git a/des/sim/verilog/tb_des.tcl b/des/sim/verilog/tb_des.tcl index 871b489..46bbb0e 100644 --- a/des/sim/verilog/tb_des.tcl +++ b/des/sim/verilog/tb_des.tcl @@ -7,5 +7,4 @@ lappend signals "tb_des.key" lappend signals "tb_des.datain" lappend signals "tb_des.validout" lappend signals "tb_des.dataout" -lappend signals "tb_des.outdex" set num_added [ gtkwave::addSignalsFromList $signals ] From 9a340f552421691f908f3945a719db49e6296e20 Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Fri, 22 Mar 2013 13:30:40 +0100 Subject: [PATCH 2/3] added timescale directive and set it to 1 ns/1 ps --- des/sim/verilog/tb_des.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/des/sim/verilog/tb_des.v b/des/sim/verilog/tb_des.v index 82df3ec..ac0429a 100644 --- a/des/sim/verilog/tb_des.v +++ b/des/sim/verilog/tb_des.v @@ -18,6 +18,8 @@ // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA // ====================================================================== +`timescale 1ns/1ps + module tb_des; From 4c7037b7c30cafea475ab54afa4f007f92a49755 Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Fri, 22 Mar 2013 13:30:59 +0100 Subject: [PATCH 3/3] added timescale directive and set it to 1 ns/1 ps --- des/rtl/verilog/des.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/des/rtl/verilog/des.v b/des/rtl/verilog/des.v index 2945bae..dd94799 100644 --- a/des/rtl/verilog/des.v +++ b/des/rtl/verilog/des.v @@ -19,6 +19,8 @@ // ====================================================================== +`timescale 1ns/1ps + module des (