From cb14f089b962bad7586e855474cd64c18ac1067d Mon Sep 17 00:00:00 2001 From: tmeissner Date: Wed, 25 Mar 2015 00:47:57 +0100 Subject: [PATCH] add acceptin & acceptout ports --- des/sim/verilog/tb_des.tcl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/des/sim/verilog/tb_des.tcl b/des/sim/verilog/tb_des.tcl index 46bbb0e..d7df8a6 100644 --- a/des/sim/verilog/tb_des.tcl +++ b/des/sim/verilog/tb_des.tcl @@ -2,9 +2,11 @@ set signals [list] lappend signals "tb_des.reset" lappend signals "tb_des.clk" lappend signals "tb_des.validin" +lappend signals "tb_des.acceptout" lappend signals "tb_des.mode" lappend signals "tb_des.key" lappend signals "tb_des.datain" lappend signals "tb_des.validout" +lappend signals "tb_des.acceptin" lappend signals "tb_des.dataout" set num_added [ gtkwave::addSignalsFromList $signals ]