diff --git a/aes/sim/vhdl/tb_aes.vhd b/aes/sim/vhdl/tb_aes.vhd
index 3fec615..1c74e09 100644
--- a/aes/sim/vhdl/tb_aes.vhd
+++ b/aes/sim/vhdl/tb_aes.vhd
@@ -19,19 +19,18 @@
 -- ======================================================================
 
 
--- Revision 0.1   2011/10/22
--- Initial release
-
 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 
+
 entity tb_aes is
 end entity tb_aes;
 
 
+
 architecture rtl of tb_aes is
 
 
@@ -46,9 +45,6 @@ architecture rtl of tb_aes is
 
 
   component aes is
-    generic (
-      ovl_enable  : boolean
-    );
     port (
       reset_i     : in  std_logic;
       clk_i       : in  std_logic;
@@ -70,9 +66,6 @@ begin
 
 
   i_aes : aes
-  generic map (
-    ovl_enable => false
-  )
   port map (
     reset_i  => s_reset,
     clk_i    => s_clk,