From f8226943a33f8d990814506ed0e37bcbc058f8ad Mon Sep 17 00:00:00 2001 From: tmeissner Date: Sat, 28 Dec 2013 01:16:23 +0100 Subject: [PATCH] changed reset & clk timing according to vhdl testbench --- cbctdes/sim/verilog/tb_cbctdes.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cbctdes/sim/verilog/tb_cbctdes.v b/cbctdes/sim/verilog/tb_cbctdes.v index 4672b64..96b44c1 100644 --- a/cbctdes/sim/verilog/tb_cbctdes.v +++ b/cbctdes/sim/verilog/tb_cbctdes.v @@ -63,11 +63,11 @@ module tb_cbctdes; initial begin reset = 1; #1 reset = 0; - #20 reset = 1; + #100 reset = 1; end - // generate clock with 100 mhz - always #5 clk = !clk; + // generate clock with 50 mhz + always #10 clk = !clk; // init the register values