From fd799eeed1540485114df4e461523ae6f96c888d Mon Sep 17 00:00:00 2001 From: tmeissner Date: Fri, 22 Mar 2013 18:27:19 +0100 Subject: [PATCH] change in error message --- des/sim/verilog/tb_des.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/des/sim/verilog/tb_des.v b/des/sim/verilog/tb_des.v index 82df3ec..d3360d5 100644 --- a/des/sim/verilog/tb_des.v +++ b/des/sim/verilog/tb_des.v @@ -98,6 +98,7 @@ module tb_des; begin @(posedge clk) // detected an error -> print error message + // increent error counter if (dataout != data_output[outdex]) begin $display ("error, output was %h - should have been %h", dataout, data_output[outdex]); errors = errors + 1; @@ -106,7 +107,7 @@ module tb_des; // simulation finished -> print messages and if an error was detected $display ("#############"); if (errors) begin - $display ("test finished, there were %0d errors detected :(", errors); + $display ("test finished, %0d errors detected :(", errors); end else begin $display ("test finished, no errors detected :)"); end