Commit Graph
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b6fdf6binitial commit of cbcdes verilog verification sources by 2013-03-28 20:24:48 +0100 -
7105d21iunitial commit os cbctdes verilog sources by 2013-03-28 20:20:13 +0100 -
67fdd7emoved in seperate directory 'vhdl' by 2013-03-26 20:43:45 +0100 -
20f0bacmoved in seperate directory 'vhdl' by 2013-03-26 20:42:15 +0100 -
0c70ec5initial commit of verilog simulation environment for verilog cbcdes core by 2013-03-25 00:18:41 +0100 -
4489748initial commit os CBCDES verilog design file by 2013-03-25 00:17:36 +0100 -
51745c4adapt to new directory structure by 2013-03-25 00:15:35 +0100 -
8c33d73moved in seperate directory 'vhdl' by 2013-03-25 00:13:02 +0100 -
cb76c16moved in seperate directory 'vhdl' by 2013-03-25 00:12:50 +0100 -
e8aff41bugfixes to make tdes.v core working correctly by 2013-03-24 23:47:30 +0100 -
5fff1d8initial commit of verilog simulation environment for tdes core by 2013-03-24 23:46:21 +0100 -
553e105Merge branch 'master' of https://github.com/tmeissner/cryptocores by 2013-03-24 17:39:09 +0100 -
e2225fbinitial commit os TDES verilog design file by 2013-03-24 16:37:16 +0100 -
45403f1import of des verilog design files by 2013-03-24 16:07:15 +0100 -
dd979b5adapt makefile to new directory structure; new variable SRC_FILES for vhdl sources by 2013-03-24 16:05:44 +0100 -
715b8b1beauty care by 2013-03-24 16:05:13 +0100 -
30a7af4moved into seperate vhdl folder by 2013-03-24 16:00:37 +0100 -
5e42292moved into seperate vhdl folder by 2013-03-24 16:00:21 +0100 -
d779f5amoved into seperate vhdl folder by 2013-03-24 15:59:10 +0100 -
7822728moved into seperate vhdl folder by 2013-03-24 15:58:51 +0100 -
c42beffmoved vhdl design files in directory 'vhdl' by 2013-03-22 23:39:14 +0100 -
ab47fd3import verilog des design files from des project by 2013-03-22 23:38:28 +0100 -
6356f62moved vhdl design files in directory 'vhdl' by 2013-03-22 23:36:57 +0100 -
09da6aecorrect some copy & paste errors in key scheduling process by 2013-03-22 23:24:10 +0100 -
734efbcadded test cases for decryption in stimuli & checker; bugfix wwith validout detection by 2013-03-22 23:23:30 +0100 -
fc78527added test data for decryption test cases by 2013-03-22 23:22:42 +0100 -
bab578fMerge branch 'master' of https://github.com/tmeissner/cryptocores by 2013-03-22 18:27:23 +0100 -
fd799eechange in error message by 2013-03-22 18:27:19 +0100 -
4c7037badded timescale directive and set it to 1 ns/1 ps by 2013-03-22 13:30:59 +0100 -
9a340f5added timescale directive and set it to 1 ns/1 ps by 2013-03-22 13:30:40 +0100 -
bd2f313removed 'outdex' reg from waveform viewer by 2013-03-22 13:30:05 +0100 -
e406823testbench enhancement by 2013-03-21 23:27:49 +0100 -
10bcd87dependency files now moved into 2 variables SRC_FILES & SIM_FILES by 2013-03-21 23:27:20 +0100 -
28542eanew verification data files key_input.txt & data_output.txt by 2013-03-21 23:26:32 +0100 -
6c9a4f1stimuli.txt moved to data_input.txt by 2013-03-21 23:25:43 +0100 -
ccf8140complete refactoring of the des verilog code by 2013-03-20 23:40:14 +0100 -
08f7c16fixed some errors in des helper functions by 2013-03-20 23:36:18 +0100 -
74c974ffurther converting of vhdl into verilog code by 2012-03-25 22:19:19 +0200 -
5bf2207splitting function ip to 2 sub functions ip0 & ip1 by 2012-03-25 16:50:59 +0200 -
270ac45began with converting of implementation from vhdl to verilog by 2012-03-25 16:50:29 +0200 -
dd01604data for stimuli / checker data by 2012-03-25 04:00:23 +0200 -
9a29954new stimuli, checker & reset processes by 2012-03-25 03:59:47 +0200 -
5fde3acadded outdex to wave view by 2012-03-25 03:59:06 +0200 -
5e6c183moved vhdl testbench files into separate directory vhdl under sim by 2012-03-25 00:15:15 +0100 -
3c878ffmoved vhdl testbench files into separate directory vhdl under sim by 2012-03-25 00:14:38 +0100 -
3399288change lib path for simulation by 2012-03-25 00:12:06 +0100 -
6c16122moved vhdl testbench files into separate directory vhdl under sim by 2012-03-25 00:10:59 +0100 -
8f2e24fnew verilog testbench, makefile & tcl-file by 2012-03-25 00:10:18 +0100 -
804a359new synchronous process for mode & valid signals by 2012-03-24 00:43:14 +0100 -
e1900a3all necessary functions are complete now by 2012-03-22 23:52:45 +0100 -
69c7fe9added functions s1 - s8 by 2012-03-22 23:27:10 +0100 -
c1f5984initial release of des function package in verilog by 2012-03-22 21:51:04 +0100 -
93186c5initial release of des verilog implementation, framework code only at the moment by 2012-03-22 20:24:50 +0100 -
7bfc136Revert "dasdsad" by 2012-03-23 14:15:00 +0100 -
3deaf48Merge branch 'master' of https://github.com/tmeissner/cryptocores by 2012-03-23 13:54:15 +0100 -
4b41ea2dasdsad by 2012-03-23 13:53:40 +0100 -
1be72c7Revert "New verily top level file of DES algorithm" by 2012-03-23 13:51:44 +0100 -
3ff9e3eNew verily top level file of DES algorithm by 2012-03-13 17:08:54 +0100 -
78db757new verily version of ads, startup code only at the moment by 2012-03-02 12:50:52 +0100 -
455bcaaovl standard enable, fixed minor bug in pkg by 2012-03-02 12:50:28 +0100 -
4f5b5a1move vhdl files into separate directories by 2012-02-28 19:38:53 +0100 -
0b1ef75Revert "move vhdl files into separate directory" by 2012-02-28 19:36:31 +0100 -
fdc730dmove vhdl files into separate directory by 2012-02-28 19:34:52 +0100 -
783633cmove vhdl simulation files into correspondent subdirectory vhdl by 2012-02-07 16:27:10 +0100 -
6737c9bpartition design in ovl and not ovl enabled by 2012-02-07 16:02:03 +0100 -
52cf1femove rtl *.vhd files to the subdirectory vhdl of rtl directory by 2012-02-07 15:08:35 +0100 -
2e948cfdivide rtl directory in 2 sub-directories: vhdl & verilog by 2012-02-07 15:07:40 +0100 -
4f926c5new function 'mixcolumns' by 2012-01-29 19:01:29 +0100 -
1cd5fccOVL support further integrated by 2012-01-29 02:25:51 +0100 -
114a4e1remove OVL support in older, finished & verified projects by 2012-01-29 02:23:21 +0100 -
8fd02d0you can now include the OVL library if you set the OVL_ENABLE flag to 1 by 2012-01-28 02:08:54 +0100 -
b003e5eyou can now include the OVL library if you set the OVL_ENABLE flag to 1 by 2012-01-27 21:42:56 +0100 -
6624df8new function invshiftrow by 2011-12-30 17:24:47 +0100 -
85be1dacorrect minor bug by 2011-12-30 16:14:43 +0100 -
b3dde95new primitive function for multiplication in 8 bit galois field by 2011-12-30 16:07:03 +0100 -
e1c4e19filled function shiftrow with functional content by 2011-12-30 14:58:39 +0100 -
c3026a1new function frame shift row, outcommented by 2011-12-30 13:13:05 +0100 -
00cd0ebnew function 'sortdata' to put input vector into internal data matrix by 2011-12-30 02:20:34 +0100 -
25cf2bfnew functions: byte sub & invbytesub by 2011-12-30 01:39:52 +0100 -
ba30457new tcl-file to control gtkwave by 2011-12-30 01:39:00 +0100 -
ac8f8ebintegrated tcl-file into gtkwave starting parameters by 2011-12-30 01:38:33 +0100 -
c5fa11fintegrated tcl-file into gtkwave starting parameters by 2011-12-30 00:18:45 +0100 -
fbd8c11integrated tcl-file into gtkwave starting parameters by 2011-12-28 23:12:14 +0100 -
36aeb55new tcl-file to control gtkwave by 2011-12-28 20:16:39 +0100 -
4aa2f20added array constants for forward & reverse s-boxes by 2011-10-26 10:48:17 +0200 -
42d69abInitial release, pre-alpha state, only framework code by 2011-10-22 00:33:49 +0200 -
2e7c021initial release of tdes in cbc mode by 2011-10-16 17:58:40 +0200 -
4b8ab0dadded async reset to des-module to avoid simulation warnings and unititialized ports by 2011-10-15 17:49:58 +0200 -
d3314a7minor updates by 2011-10-08 02:00:03 +0200 -
e1c9cb2fixed some bugs with the key suppliment by 2011-10-08 01:59:38 +0200 -
aec8130some minor bugfixes by 2011-10-08 01:31:07 +0200 -
a288199initial release of testbench and makefile by 2011-10-08 01:30:46 +0200 -
25f37f7Revision 0.1 2011/10/08 by 2011-10-08 00:39:21 +0200 -
2a0a934Revision 0.1 2011/10/08 by 2011-10-08 00:38:22 +0200 -
5f440e1Revision 0.2 2011/10/06 by 2011-10-06 00:08:58 +0200 -
5e4bd28added basic verification of cbc ability by 2011-10-06 00:08:30 +0200 -
f0cba7eexpanded simulation time to 220us by 2011-10-06 00:07:56 +0200 -
80f6b63Revert 32e44bdf948f5fc3a420a37defe918ec55d67b6a^..HEAD by 2011-10-05 22:20:47 +0200 -
32e44bdRevision 1.2 2011/10/05 by 2011-10-05 22:20:16 +0200 -
5b924ffexpanded simulation time to 200 us for decryption testcases by 2011-10-05 22:18:46 +0200