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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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211
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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umarcor
17ce27949f
ci: rename 'test' workflow to 'Simulation'
3 years ago
..
workflows
ci: rename 'test' workflow to 'Simulation'
3 years ago
test.sh
CTR-AES: Fix counter incr & init; add 1st simple testbench
3 years ago