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169 lines
5.2 KiB
169 lines
5.2 KiB
-- ======================================================================
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-- AES encryption/decryption
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-- Copyright (C) 2019 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- ======================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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use std.env.all;
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use work.aes_pkg.all;
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entity tb_aes is
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end entity tb_aes;
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architecture rtl of tb_aes is
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signal s_reset : std_logic := '0';
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signal s_clk : std_logic := '0';
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signal s_mode : std_logic := '0';
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signal s_key : std_logic_vector(0 to 127) := (others => '0');
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signal s_datain : std_logic_vector(0 to 127) := (others => '0');
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signal s_validin_enc : std_logic := '0';
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signal s_acceptout_enc : std_logic;
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signal s_dataout_enc : std_logic_vector(0 to 127);
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signal s_validout_enc : std_logic;
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signal s_acceptin_enc : std_logic := '0';
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signal s_validin_dec : std_logic := '0';
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signal s_acceptout_dec : std_logic;
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signal s_dataout_dec : std_logic_vector(0 to 127);
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signal s_validout_dec : std_logic;
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signal s_acceptin_dec : std_logic := '0';
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procedure cryptData(datain : in std_logic_vector(0 to 127);
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key : in std_logic_vector(0 to 127);
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mode : in boolean;
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dataout : out std_logic_vector(0 to 127);
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bytelen : in integer) is
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begin
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report "VHPIDIRECT cryptData" severity failure;
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end procedure;
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attribute foreign of cryptData: procedure is "VHPIDIRECT cryptData";
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function swap (datain : std_logic_vector(0 to 127)) return std_logic_vector is
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variable v_data : std_logic_vector(0 to 127);
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begin
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for i in 0 to 15 loop
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for y in 0 to 7 loop
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v_data((i*8)+y) := datain((i*8)+7-y);
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end loop;
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end loop;
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return v_data;
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end function;
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begin
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s_clk <= not(s_clk) after 10 ns;
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s_reset <= '1' after 100 ns;
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i_aes_enc : aes_enc
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port map (
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reset_i => s_reset,
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clk_i => s_clk,
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key_i => s_key,
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data_i => s_datain,
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valid_i => s_validin_enc,
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accept_o => s_acceptout_enc,
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data_o => s_dataout_enc,
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valid_o => s_validout_enc,
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accept_i => s_acceptin_enc
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);
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i_aes_dec : aes_dec
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port map (
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reset_i => s_reset,
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clk_i => s_clk,
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key_i => s_key,
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data_i => s_datain,
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valid_i => s_validin_dec,
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accept_o => s_acceptout_dec,
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data_o => s_dataout_dec,
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valid_o => s_validout_dec,
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accept_i => s_acceptin_dec
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);
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process is
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variable v_key : std_logic_vector(0 to 127);
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variable v_datain : std_logic_vector(0 to 127);
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variable v_dataout : std_logic_vector(0 to 127);
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variable v_random : RandomPType;
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begin
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v_random.InitSeed(v_random'instance_name);
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wait until s_reset = '1';
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-- ENCRYPTION TESTs
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report "Test encryption";
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for i in 0 to 63 loop
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wait until rising_edge(s_clk);
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s_validin_enc <= '1';
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v_key := v_random.RandSlv(128);
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v_datain := v_random.RandSlv(128);
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s_key <= v_key;
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s_datain <= v_datain;
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cryptData(swap(v_datain), swap(v_key), true, v_dataout, v_datain'length/8);
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wait until s_acceptout_enc = '1' and rising_edge(s_clk);
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s_validin_enc <= '0';
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wait until s_validout_enc = '1' and rising_edge(s_clk);
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s_acceptin_enc <= '1';
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assert s_dataout_enc = swap(v_dataout)
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report "Encryption error"
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severity failure;
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wait until rising_edge(s_clk);
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s_acceptin_enc <= '0';
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end loop;
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-- DECRYPTION TESTs
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report "Test decryption";
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for i in 0 to 63 loop
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wait until rising_edge(s_clk);
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s_validin_dec <= '1';
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v_key := x"2b7e151628aed2a6abf7158809cf4f3c";
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v_datain := v_random.RandSlv(128);
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s_key <= v_key;
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s_datain <= v_datain;
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cryptData(swap(v_datain), swap(v_key), false, v_dataout, v_datain'length/8);
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wait until s_acceptout_dec = '1' and rising_edge(s_clk);
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s_validin_dec <= '0';
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wait until s_validout_dec = '1' and rising_edge(s_clk);
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s_acceptin_dec <= '1';
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assert s_dataout_dec = swap(v_dataout)
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report "Decryption error"
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severity failure;
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wait until rising_edge(s_clk);
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s_acceptin_dec <= '0';
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end loop;
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wait for 100 ns;
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report "Tests successful";
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finish(0);
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end process;
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end architecture rtl;
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