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cryptocores
Cryptography IP-cores & tests written in VHDL / Verilog
The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.
The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation.
HINT:
The tests of some algorithms use the OSVVM library, which is redistributed as
submodule. To get & initialize the submodule, please use the --recursive option
when cloning this repository.