tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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6 years ago

[options]
mode prove
#mode bmc
#depth 20

[engines]
smtbmc

[script]
verific -vhdl alu.vhd
verific -formal alu_t.sv
prep -top alu_t

[files]
alu.vhd
alu_t.sv