diff --git a/vai_reg/properties.sv b/vai_reg/properties.sv
index 79d610f..10853fd 100644
--- a/vai_reg/properties.sv
+++ b/vai_reg/properties.sv
@@ -13,7 +13,9 @@ module properties (
     input       DoutAccept_i,
     // Internals
     input [2:0] s_fsm_state,
-    input [7:0] s_header
+    input [7:0] s_header,
+    input       s_error,
+    input [7:0] s_register [0:7]
 );
 
 
@@ -33,13 +35,22 @@ module properties (
   always @(posedge Clk_i)
     init_state = 0;
 
+  // Default clocking & reset
+
   default clocking
     @(posedge Clk_i);
   endclocking
 
+  default disable iff (!Reset_n_i);
+
 
   // Constraints
 
+  assume property (
+    DinValid_i && !DinAccept_o |=>
+    $stable(DinValid_i)
+  );
+
   assume property (
     DinValid_i && !DinAccept_o |=>
     $stable(Din_i)
@@ -90,33 +101,33 @@ module properties (
 
   // State changes
 
-  assert property (disable iff (!Reset_n_i)
+  assert property (
     s_fsm_state == 0 |=> s_fsm_state == 1
   );
 
-  assert property (disable iff (!Reset_n_i)
+  assert property (
     s_fsm_state == 1 && DinValid_i && DinStart_i && DinStop_i && Din_i[3:0] == `READ |=>
     s_fsm_state == 2
   );
 
-  assert property (disable iff (!Reset_n_i)
+  assert property (
     s_fsm_state == 1 && DinValid_i && DinStart_i && !DinStop_i && Din_i[3:0] == `WRITE |=>
     s_fsm_state == 3
   );
 
-  assert property (disable iff (!Reset_n_i)
+  assert property (
     s_fsm_state == 2 |=> s_fsm_state == 4
   );
 
-  assert property (disable iff (!Reset_n_i)
+  assert property (
     s_fsm_state == 4 && DoutValid_o && DoutAccept_i && s_header[3:0] == `READ |=> s_fsm_state == 5
   );
 
-  assert property (disable iff (!Reset_n_i)
+  assert property (
     s_fsm_state == 4 && DoutValid_o && DoutAccept_i && s_header[3:0] != `READ |=> s_fsm_state == 6
   );
 
-  assert property (disable iff (!Reset_n_i)
+  assert property (
     s_fsm_state == 6 && DoutValid_o && DoutAccept_i |=> s_fsm_state == 0
   );
 
@@ -128,11 +139,31 @@ module properties (
     s_header[3:0] inside {`READ, `WRITE}
   );
 
+  assert property (
+    s_fsm_state > 1 |=>
+    $stable(s_header)
+  );
+
   assert property (
     DoutStart_o && DoutValid_o |->
     Dout_o[3:0] == s_header[3:0]
   );
 
+  assert property (
+    s_fsm_state inside {1, 2, 3} |->
+    !s_error
+  );
+
+  assert property (
+    s_fsm_state >= 4 |->
+    s_error == !(s_header[7:4] <= 7)
+  );
+
+  assert property (
+    DoutStop_o && DoutValid_o |->
+    Dout_o == s_error
+  );
+
   assert property (
     DoutValid_o && !DoutAccept_i |=>
     $stable(Dout_o)
@@ -164,6 +195,32 @@ module properties (
     DoutValid_o |-> s_fsm_state >= 4 && s_fsm_state <= 6
   );
 
+  // Write ack frame
+  assert property (
+    DoutValid_o && DoutStart_o && DoutAccept_i && Dout_o[3:0] == `WRITE |=>
+    !DoutValid_o ##1
+    DoutValid_o && DoutStop_o
+  );
+
+  // Read ack frame
+  assert property (
+    DoutValid_o && DoutStart_o && DoutAccept_i && Dout_o[3:0] == `READ |=>
+    !DoutValid_o ##1
+    DoutValid_o && !DoutStart_o && !DoutStop_o && !DoutAccept_i [*] ##1
+    DoutValid_o && !DoutStart_o && !DoutStop_o && DoutAccept_i ##1
+    !DoutValid_o ##1
+    DoutValid_o && DoutStop_o
+  );
+
+  // Can only be proven with abc at the moment
+  // smtbmc fails with unbounded proof
+  assert property (
+    s_fsm_state == 1 && DinValid_i && DinStart_i && !DinStop_i && DinAccept_o && Din_i[3:0] == `WRITE && Din_i[7:4] <= 7 ##1
+    !DinValid_i [*] ##1
+    s_fsm_state == 3 && DinValid_i && DinAccept_o && DinStop_i  |=>
+    s_register[s_header[7:4]] == $past(Din_i)
+  );
+
 
 endmodule
 
diff --git a/vai_reg/trace.gtkw b/vai_reg/trace.gtkw
new file mode 100644
index 0000000..556070f
--- /dev/null
+++ b/vai_reg/trace.gtkw
@@ -0,0 +1,43 @@
+[*]
+[*] GTKWave Analyzer v3.3.91 (w)1999-2018 BSI
+[*] Sat Dec 29 18:53:51 2018
+[*]
+[dumpfile_size] 13145
+[timestart] 0
+[size] 1344 495
+[pos] -1 -1
+*-5.329921 40 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] vai_reg.
+[sst_width] 193
+[signals_width] 199
+[sst_expanded] 1
+[sst_vpaned_height] 130
+@28
+vai_reg.properties.Clk_i
+@200
+-VAI req
+@28
+vai_reg.properties.DinStart_i
+vai_reg.properties.DinStop_i
+@22
+vai_reg.properties.Din_i[7:0]
+@28
+vai_reg.properties.DinValid_i
+vai_reg.properties.DinAccept_o
+@200
+-VAI ack
+@28
+vai_reg.properties.DoutStart_o
+vai_reg.properties.DoutStop_o
+@22
+vai_reg.properties.Dout_o[7:0]
+@28
+vai_reg.properties.DoutValid_o
+vai_reg.properties.DoutAccept_i
+@200
+-Internal
+@28
+vai_reg.properties.s_fsm_state[2:0]
+vai_reg.properties.s_register[63:0]
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/vai_reg/vai_reg.vhd b/vai_reg/vai_reg.vhd
index 41975a7..c497db8 100644
--- a/vai_reg/vai_reg.vhd
+++ b/vai_reg/vai_reg.vhd
@@ -79,18 +79,19 @@ begin
           s_header    <= (others => '0');
           s_data      <= (others => '0');
           s_error     <= false;
+          DinAccept_o <= '1';
           s_fsm_state <= GET_HEADER;
 
         when GET_HEADER =>
-          DinAccept_o <= '1';
           if (DinValid_i = '1' and DinStart_i = '1') then
-            DinAccept_o <= '0';
             s_header    <= Din_i;
             if (Din_i(3 downto 0) = C_READ and DinStop_i = '1') then
+              DinAccept_o <= '0';
               s_fsm_state <= GET_DATA;
             elsif (Din_i(3 downto 0) = C_WRITE and DinStop_i = '0') then
               s_fsm_state <= SET_DATA;
             else
+              DinAccept_o <= '0';
               s_fsm_state <= IDLE;
             end if;
           end if;
@@ -105,16 +106,11 @@ begin
           s_fsm_state <= SEND_HEADER;
 
         when SET_DATA =>
-          DinAccept_o <= '1';
           if (DinValid_i = '1') then
             DinAccept_o <= '0';
             if (DinStop_i = '1') then
               if (unsigned(a_addr) <= 7) then
-                -- Following line results in a Segmentation Fault
                 s_register(to_integer(unsigned(a_addr))) <= Din_i;
-                -- Following line results in following error:
-                -- ERROR: Unsupported cell type $dlatchsr for cell $verific$wide_dlatchrs_8.$verific$i1$172.
-                s_register(0) <= Din_i;
               else
                 s_error <= true;
               end if;