commit 4feec0fff6eee37a3ed1b5533461dd59da42620b Author: tmeissner Date: Sun Nov 11 19:15:03 2018 +0100 Inital commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..c0e8fb5 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +work/* \ No newline at end of file diff --git a/LICENSE.md b/LICENSE.md new file mode 100644 index 0000000..ba76508 --- /dev/null +++ b/LICENSE.md @@ -0,0 +1,166 @@ +#GNU LESSER GENERAL PUBLIC LICENSE +Version 3, 29 June 2007 + + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + +#### 0. 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Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. + + Each version is given a distinguishing version number. If the +Library as you received it specifies that a certain numbered version +of the GNU Lesser General Public License "or any later version" +applies to it, you have the option of following the terms and +conditions either of that published version or of any later version +published by the Free Software Foundation. If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. diff --git a/README.md b/README.md new file mode 100644 index 0000000..cd1b1e8 --- /dev/null +++ b/README.md @@ -0,0 +1,6 @@ +# formal_verification + +Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a free formal verification tool based on Yosys. Some examples use the VHDL/SystemVerilog parser plugin by Verific which isn't free SW and nit included in the free Yosys version. See on the [Symbiotic EDA website](https://www.symbioticeda.com) for more information. + +### alu +A simple ALU design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple properties for assert & cover directives which are proved with the SymbiYosys tool. \ No newline at end of file diff --git a/alu/.gitignore b/alu/.gitignore new file mode 100644 index 0000000..26ad522 --- /dev/null +++ b/alu/.gitignore @@ -0,0 +1 @@ +*/work/* \ No newline at end of file diff --git a/alu/Makefile b/alu/Makefile new file mode 100644 index 0000000..b6df3b0 --- /dev/null +++ b/alu/Makefile @@ -0,0 +1,2 @@ +alu: alu.vhd alu_t.v alu_f.sby + sby -f -d work alu_f.sby diff --git a/alu/alu.vhd b/alu/alu.vhd new file mode 100644 index 0000000..f77e468 --- /dev/null +++ b/alu/alu.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + + +entity alu is + port ( + Reset_n_i : in std_logic; + Clk_i : in std_logic; + Opc_i : in std_logic_vector(1 downto 0); + DinA_i : in std_logic_vector(31 downto 0); + DinB_i : in std_logic_vector(31 downto 0); + Dout_o : out std_logic_vector(31 downto 0); + OverFlow_o : out std_logic + ); +end entity alu; + + + +architecture rtl of alu is + + + constant c_add : std_logic_vector(1 downto 0) := "00"; + constant c_sub : std_logic_vector(1 downto 0) := "01"; + constant c_and : std_logic_vector(1 downto 0) := "10"; + constant c_or : std_logic_vector(1 downto 0) := "11"; + + +begin + + + process (Reset_n_i, Clk_i) is + begin + if (Reset_n_i = '0') then + Dout_o <= (others => '0'); + elsif (rising_edge(Clk_i)) then + case Opc_i is + when c_add => (OverFlow_o, Dout_o) <= + std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) + + resize(unsigned(DinB_i), Dout_o'length+1)); + when c_sub => (OverFlow_o, Dout_o) <= + std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) - + resize(unsigned(DinB_i), Dout_o'length+1)); + when c_and => Dout_o <= DinA_i and DinB_i; + when c_or => Dout_o <= DinA_i or DinB_i; + when others => null; + end case; + end if; + end process; + + +end architecture rtl; + diff --git a/alu/alu_f.sby b/alu/alu_f.sby new file mode 100644 index 0000000..9ed894a --- /dev/null +++ b/alu/alu_f.sby @@ -0,0 +1,16 @@ +[options] +mode prove +#mode bmc +#depth 20 + +[engines] +smtbmc + +[script] +verific -vhdl alu.vhd +verific -formal alu_t.sv +prep -top alu_t + +[files] +alu.vhd +alu_t.sv diff --git a/alu/alu_t.sv b/alu/alu_t.sv new file mode 100644 index 0000000..6b35426 --- /dev/null +++ b/alu/alu_t.sv @@ -0,0 +1,57 @@ +module alu_t ( + inout Reset_n_i, + input Clk_i, + input [1:0] Opc_i, + input [31:0] DinA_i, + input [31:0] DinB_i, + output [31:0] Dout_o, + output OverFlow_o +); + + + alu alu_i ( + .Reset_n_i(Reset_n_i), + .Clk_i(Clk_i), + .Opc_i(Opc_i), + .DinA_i(DinA_i), + .DinB_i(DinB_i), + .Dout_o(Dout_o), + .OverFlow_o(OverFlow_o) + ); + + const logic [1:0] OPC_ADD = 0; + const logic [1:0] OPC_SUB = 1; + const logic [1:0] OPC_AND = 2; + const logic [1:0] OPC_OR = 3; + + initial begin + assume (!Reset_n_i); + end + + bit unsigned [32:0] dina, dinb; + + assign dina = DinA_i; + assign dinb = DinB_i; + + assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_ADD |=> Dout_o == ($past(DinA_i) + $past(DinB_i))); + assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_ADD && (dina + dinb) > 2**32-1 |=> OverFlow_o); + assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_SUB |=> Dout_o == ($past(DinA_i) - $past(DinB_i))); + assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_SUB && (dina - dinb) > 2**32-1 |=> OverFlow_o); + assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_AND |=> Dout_o == ($past(DinA_i) & $past(DinB_i))); + assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_OR |=> Dout_o == ($past(DinA_i) | $past(DinB_i))); + + assert property (@(posedge Clk_i or negedge Clk_i) !Reset_n_i |-> Dout_o == 0); + + property cover_opc (opc); + @(posedge Clk_i) + disable iff (!Reset_n_i) Opc_i == opc; + endproperty + + cover property (cover_opc(OPC_ADD)); + cover property (cover_opc(OPC_SUB)); + cover property (cover_opc(OPC_AND)); + cover property (cover_opc(OPC_OR)); + + +endmodule +