From 641fa3a6b47ff648f0c2f78d4eb71241d7e3c81b Mon Sep 17 00:00:00 2001 From: tmeissner Date: Thu, 4 Feb 2021 01:02:20 +0100 Subject: [PATCH] Add fwft-fifo info to readme --- README.md | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 4d87876..29fb6bd 100644 --- a/README.md +++ b/README.md @@ -24,8 +24,11 @@ A simple counter design in VHDL. The testbench contains various simple propertie ### fifo A simple synchronous FIFO with various checks for write/read pointers, data and flags. +### fwft_fifo +A simple synchronous FIFO with first-word fall-through behaviour. Uses fifo as sub-unit. This design serves as an example how to verify designs with sub-units containing formal checks. + ### vai_fifo -A simple FIFO with valid-accept-interface. Consists of fifo as sub-unit and some glue logic doing fifo<->vai interface conversion. This design serves as an example how to verify designs with sub-units containing formal checks. +A simple FIFO with valid-accept interface. Consists of fwft_fifo as sub-unit and some glue logic doing fifo<->vai interface conversion. This design serves as an example how to verify designs with sub-units containing formal checks. ### vai_reg -A simple register file with VAI (valid-accept-interface) which serves as test design to try formal verification of FSMs. +A simple register file with VAI (valid-accept interface) which serves as test design to try formal verification of FSMs.