From 6d230226f26f43afda045b0fc1f6dbd6f69c51d0 Mon Sep 17 00:00:00 2001 From: Torsten Meissner Date: Wed, 14 Nov 2018 12:31:59 +0100 Subject: [PATCH] Add info about git repo --- README.md | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/README.md b/README.md index 95bdf64..0d69da4 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,17 @@ +The original repository is located on my own git-server at [https://git.goodcleanfun.de/tmeissner/formal_verification](https://git.goodcleanfun.de/tmeissner/formal_verification) +It is mirrored to github with every push, so both should be in sync. + + # formal_verification Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a front-end for formal verification flows based on [Yosys](https://github.com/YosysHQ). Some examples use the VHDL/SystemVerilog parser plugin by Verific which isn't free SW and not included in the free Yosys version. See on the [Symbiotic EDA website](https://www.symbioticeda.com) for more information. ### alu A simple ALU design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple SVA properties used by assert & cover directives which are proved with the SymbiYosys tool. + + +### counter +A simple counter design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple SVA properties used by assert & cover directives which are proved with the SymbiYosys tool. + +### dlatch +A simple test design which generates the `Unsupported cell type $dlatchsr` error using with Verific plugin.