From b48e99c1f0e73c9429ab8134b08fde7f1b34a61b Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Wed, 2 Jan 2019 11:03:50 +0100
Subject: [PATCH] Simplify signal generation

---
 vai_reg/vai_reg.vhd | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/vai_reg/vai_reg.vhd b/vai_reg/vai_reg.vhd
index c497db8..16a499b 100644
--- a/vai_reg/vai_reg.vhd
+++ b/vai_reg/vai_reg.vhd
@@ -50,8 +50,7 @@ architecture rtl of vai_reg is
 begin
 
 
-  s_dout_accepted <= true when DoutValid_o = '1' and DoutAccept_i = '1' else
-                     false;
+  s_dout_accepted <= (DoutValid_o and DoutAccept_i) = '1';
 
 
   process (Reset_n_i, Clk_i) is