From db4cdea24a2123a7d1ffeb0d632b03d568b21331 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Wed, 6 Jan 2021 17:02:16 +0100 Subject: [PATCH] Name assume & restrict directives --- fifo/fifo.vhd | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/fifo/fifo.vhd b/fifo/fifo.vhd index fef550d..a3953d1 100644 --- a/fifo/fifo.vhd +++ b/fifo/fifo.vhd @@ -108,10 +108,13 @@ begin default clock is rising_edge(Clk_i); -- Initial reset - restrict {not Reset_n_i[*3]; Reset_n_i[+]}[*1]; + RESTRICT_RESET : restrict + {not Reset_n_i[*3]; Reset_n_i[+]}[*1]; -- Inputs are low during reset for simplicity - assume always not Reset_n_i -> not Wen_i and not Ren_i; + ASSUME_INPUTS_DURING_RESET : assume always + not Reset_n_i -> + not Wen_i and not Ren_i; -- Asynchronous (unclocked) Reset asserts