diff --git a/README.md b/README.md
index 9906e5f..c810cb1 100644
--- a/README.md
+++ b/README.md
@@ -17,5 +17,8 @@ A simple ALU design in VHDL. The formal checks contain various simple properties
 ### counter
 A simple counter design in VHDL. The testbench contains various simple properties used by assert & cover directives which are proved with the SymbiYosys tool.
 
+### fifo
+A simple synchronous FIFO with various checks for write/read pointers, data and flags.
+
 ### vai_reg
 A simple register file with VAI (valid-accept-interface) which serves as test design to try formal verification of FSMs.
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