From f2e4f71292dad7ae3c28937fb217a4e65ea9797e Mon Sep 17 00:00:00 2001 From: tmeissner Date: Mon, 10 Aug 2020 17:13:24 +0200 Subject: [PATCH] Add infos about fifo model to README --- README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README.md b/README.md index 9906e5f..c810cb1 100644 --- a/README.md +++ b/README.md @@ -17,5 +17,8 @@ A simple ALU design in VHDL. The formal checks contain various simple properties ### counter A simple counter design in VHDL. The testbench contains various simple properties used by assert & cover directives which are proved with the SymbiYosys tool. +### fifo +A simple synchronous FIFO with various checks for write/read pointers, data and flags. + ### vai_reg A simple register file with VAI (valid-accept-interface) which serves as test design to try formal verification of FSMs. \ No newline at end of file