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The original repository is located on my own git-server at [https://git.goodcleanfun.de/tmeissner/formal_hw_verification](https://git.goodcleanfun.de/tmeissner/formal_hw_verification)

It is mirrored to github with every push, so both should be in sync.


# formal_hw_verification

Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with [SymbiYosys](https://github.com/YosysHQ/SymbiYosys), a front-end for formal verification flows based on [Yosys](https://github.com/YosysHQ/yosys).

All stuff in the master branch uses [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin) and [GHDL](https://github.com/ghdl/ghdl) as VHDL front-end plugin for (Symbi)Yosys. Using GHDL as synthesis frontend allows using PSL as verification language.

Some examples in the [verific branch](https://github.com/tmeissner/formal_hw_verification/tree/verific) use the commercial VHDL/SystemVerilog frontend plugin by Verific which isn't free SW. It's included in the Tabby CAD Suite but not in the free Yosys version. See on the [Yosys HQ website](https://www.yosyshq.com/products-and-services) for more information.

You can use the `hdlc/formal:all` docker image provided by the [hdl containers project](https://hdl.github.io/containers/) (recommended). Or you build a docker image on your own machine using my [Dockerfiles for SymbiYosys & GHDL](https://github.com/tmeissner/Dockerfiles). With both you have the latest tool versions available.

### alu
A simple ALU design in VHDL. The formal checks contain various simple properties used by assert & cover directives which are proved with the SymbiYosys tool.

### counter
A simple counter design in VHDL. The testbench contains various simple properties used by assert & cover directives which are proved with the SymbiYosys tool.

### fifo
A simple synchronous FIFO with various checks for write/read pointers, data and flags.

### fwft_fifo
A simple synchronous FIFO with first-word fall-through behaviour. Uses fifo as sub-unit. This design serves as an example how to verify designs with sub-units containing formal checks.

### vai_fifo
A simple FIFO with valid-accept interface. Consists of fwft_fifo as sub-unit and some glue logic doing fifo<->vai interface conversion. This design serves as an example how to verify designs with sub-units containing formal checks.

### vai_reg
A simple register file with VAI (valid-accept interface) which serves as test design to try formal verification of FSMs.