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81 lines
1.5 KiB
81 lines
1.5 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vai_fifo is
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generic (
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Formal : boolean := true;
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Depth : positive := 16;
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Width : positive := 16
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);
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port (
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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-- write
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Valid_i : in std_logic;
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Accept_o : out std_logic;
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Din_i : in std_logic_vector(Width-1 downto 0);
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-- read
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Valid_o : out std_logic;
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Accept_i : in std_logic;
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Dout_o : out std_logic_vector(Width-1 downto 0)
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);
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end entity vai_fifo;
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architecture rtl of vai_fifo is
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signal s_wen : std_logic;
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signal s_ren : std_logic;
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signal s_full : std_logic;
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signal s_empty : std_logic;
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begin
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i_fifo : entity work.fifo
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generic map (
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Formal => Formal,
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Depth => Depth,
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Width => Width
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)
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port map (
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Reset_n_i => Reset_n_i,
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Clk_i => Clk_i,
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-- write
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Wen_i => s_wen,
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Din_i => Din_i,
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Full_o => s_full,
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Werror_o => open,
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-- read
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Ren_i => s_ren,
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Dout_o => Dout_o,
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Empty_o => s_empty,
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Rerror_o => open
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);
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s_wen <= Valid_i and not s_full;
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s_ren <= Accept_i and not s_empty;
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Accept_o <= not s_full;
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Valid_o <= not s_empty;
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FormalG : if Formal generate
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default clock is rising_edge(Clk_i);
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-- Inputs are low during reset for simplicity
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vai_fifo_reset_a : assume always not Reset_n_i -> not Valid_i and not Accept_i;
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end generate FormalG;
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end architecture rtl;
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