tmeissner/formal_hw_verification: Trying to verify Verilog/VHDL designs with formal methods and tools - .github/generate_matrix.sh at 37619d21ab27ccdee34780a6be6514326348a120 - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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 								#!/usr/bin/env bash
 								_matrix=''
 								for item in $(cat tests.txt); do
 								  _matrix+="'$item', "
 								done
 								echo "::set-output name=matrix::[$_matrix]"