Trying to verify Verilog/VHDL designs with formal methods and tools
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19 lines
231 B

[options]
depth 30
wait on
mode prove
#mode bmc
[engines]
smtbmc
abc pdr
[script]
verific -vhdl vai_reg.vhd
verific -formal properties.sv
verific -import -extnets -all vai_reg
prep -top vai_reg
[files]
vai_reg.vhd
properties.sv